公开(公告)号：US10817178B2

公开(公告)日：2020-10-27

申请号：US15032327

申请日：2013-10-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jichuan Chang ,  Sheng Li ,  Parthasarathy Ranganathan

IPC: G06F3/06

Abstract: A method for compressing and compacting memory on a memory device is described. The method includes organizing a number of compressed memory pages referenced in a number of compaction table entries based on a size of the number of compressed memory pages and compressing the number of compaction table entries, in which a compaction table entry comprise a number of fields.

公开(公告)号：US10572150B2

公开(公告)日：2020-02-25

申请号：US14784245

申请日：2013-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sheng Li ,  Norman Paul Jouppi ,  Paolo Faraboschi ,  Michael R. Krause

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/38 ,  G06F12/08 ,  G06F11/20 ,  G06F11/34 ,  G06F12/0811

Abstract: According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.

公开(公告)号：US10331560B2

公开(公告)日：2019-06-25

申请号：US15113960

申请日：2014-01-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jichuan Chang ,  Sheng Li

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/1027

Abstract: Methods and systems for providing cache coherence in multi-compute-engine systems are described herein. In on example, concise cache coherency directory (CDir) for providing cache coherence in the multi-compute-engine systems is described. The CDir comprises a common pattern aggregated entry for one or more cache lines from amongst a plurality of cache lines of a shared memory. The one or more cache lines that correspond to the common pattern aggregated entry are associated with a common sharing pattern from amongst a predetermined number of sharing patterns that repeat most frequently in the region.

公开(公告)号：US20170046395A1

公开(公告)日：2017-02-16

申请号：US15305960

申请日：2014-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sheng Li ,  Kevin T. Lim ,  Dejan S. Milojicic ,  Paolo Faraboschi

IPC: G06F17/30 ,  G06F3/06

CPC classification number: G06F17/30495 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0673 ,  G06F17/30097 ,  G06F17/3033 ,  G06F17/30584

Abstract: A bit vector for a Bloom filter is determined by performing one or more hash function operations on a set of ternary content addressable memory (TCAM) words. A TCAM array is partitioned into a first portion to store the bit vector for the Bloom filter and a second portion to store the set of TCAM words. The TCAM array can be searched using a search word by performing the one or more hash function operations on the search word to generate a hashed search word and determining whether bits at specified positions of the hashed search word match bits at corresponding positions of the bit vector stored in the first portion of the TCAM array before searching the second portion of the TCAM array with the search word.

Abstract translation: 通过对一组三元内容可寻址存储器（TCAM）字进行一个或多个散列函数操作来确定布隆过滤器的位向量。 将TCAM阵列划分为第一部分以存储布隆过滤器的位向量，以及存储该组TCAM字的第二部分。 可以使用搜索词搜索TCAM阵列，通过对搜索词执行一个或多个哈希函数操作来产生散列搜索词，并确定散列搜索词的指定位置的比特是否与比特向量的相应位置的比特匹配 存储在TCAM阵列的第一部分中，然后用搜索词搜索TCAM阵列的第二部分。

公开(公告)号：US20160275014A1

公开(公告)日：2016-09-22

申请号：US15032329

申请日：2013-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kevin T. Lim ,  Sheng Li ,  Parthasarathy Ranganathan ,  William C. Hallowell

IPC: G06F12/08 ,  G06F3/06

Abstract: According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.

Abstract translation: 根据示例，处理器生成存储器访问请求并将存储器访问请求发送到存储器模块。 当用于存储器访问请求的存储器模块中的存储器设备忙并且不能执行存储器访问请求时，处理器响应于存储器访问请求从存储器模块接收数据。

公开(公告)号：US10691344B2

公开(公告)日：2020-06-23

申请号：US14785120

申请日：2013-05-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Doe Hyun Yoon ,  Sheng Li ,  Jichuan Chang ,  Ke Chen ,  Parthasarathy Ranganathan ,  Norman Paul Jouppi

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.

公开(公告)号：US10318365B2

公开(公告)日：2019-06-11

申请号：US14437684

申请日：2012-11-02

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sheng Li ,  Norman P. Jouppi ,  Doe Hyun Yoon

IPC: G06F11/00 ,  G06F11/07 ,  G11C29/42 ,  G11C29/02 ,  G11C29/52 ,  G06F11/10 ,  G06F12/0875 ,  G11C7/20 ,  G11C29/04

Abstract: Example methods, systems, and apparatus to provide selective memory error protection and memory access granularity are disclosed herein. An example system includes a memory controller to determine a selected memory mode based on a request. The memory mode indicates that a memory page is to store a corresponding type of error protection information and is to store data for retrieval using a corresponding access granularity. The memory controller is to store the data and the error protection information in the memory page for retrieval using the error protection information and the access granularity.

公开(公告)号：US20170013060A1

公开(公告)日：2017-01-12

申请号：US15113976

申请日：2014-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Jichuan Chang ,  Sheng Li ,  Michael R. Krause

IPC: H04L29/08

CPC classification number: H04L67/1097 ,  G06F16/23 ,  G06F16/25 ,  G06F16/258 ,  H04L61/6022

Abstract: Methods and systems for communication in a heterogeneous distributed system are described. The described systems implement the described methods, where the method includes receiving data from at least one data source, by a data store computing device. The method further includes identifying a data source from amongst the at least one data source to have generated the data, based on host parameters associated with the data source and the data. Further, the method includes determining the data to be represented in a first data presentation based on the identified data source and the host parameters and transforming the data from the first data presentation to a second data presentation, where the data store computing device operates using the second data presentation.

Abstract translation: 描述了异构分布式系统中通信的方法和系统。 所描述的系统实现所描述的方法，其中该方法包括由数据存储计算设备从至少一个数据源接收数据。 该方法还包括基于与数据源和数据相关联的主机参数从至少一个数据源中识别数据源以生成数据。 此外，该方法包括基于所识别的数据源和主机参数确定要在第一数据呈现中表示的数据，并将数据从第一数据呈现转换为第二数据呈现，其中数据存储计算设备使用 第二次数据呈现。

公开(公告)号：US20160342351A1

公开(公告)日：2016-11-24

申请号：US15113824

申请日：2014-01-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sheng Li ,  Jishen Zhao ,  Jichuan Chang ,  Parthasarathy Ranganathan ,  Alistair Veitch ,  Kevin T. Lim ,  Mark Lillibridge

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1471 ,  G06F11/1474 ,  G06F2201/805 ,  G11B27/36

Abstract: A technique includes acquiring a plurality of write requests from at least one memory controller and logging information associated with the plurality of write requests in persistent storage. The technique includes applying the plurality of write requests atomically as a group to persistent storage.

Abstract translation: 一种技术包括从至少一个存储器控制器获取多个写入请求，并在永久存储器中记录与多个写入请求相关联的信息。 该技术包括将多个写请求作为一组原子地应用于持久存储。

公开(公告)号：US20160267015A1

公开(公告)日：2016-09-15

申请号：US15031181

申请日：2013-10-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sheng Li ,  Jishen Zhao ,  Jichuan Chang ,  Parthasarathy Ranganathan ,  Alistair Veitch ,  Kevin T. Lim

IPC: G06F12/10

CPC classification number: G06F12/109 ,  G06F12/10 ,  G06F2212/1041 ,  G06F2212/152 ,  G06F2212/657

Abstract: A method for mapping virtual memory pages to physical memory pages is described. The method includes receiving a mapping of a virtual memory page to multiple physical memory pages, detecting a request for a transaction to be performed on data contained in the multiple physical memory pages, in which the transaction includes a number of data updates, determining which of the number of multiple physical memory pages contains a latest version of the data to be updated by the transaction, updating a physical memory page by performing the transaction within a physical memory page among the multiple physical memory pages that does not contain the latest version of the data, and updating an indication of which of the physical memory pages contains the latest version of the data pertaining to the transaction.

Abstract translation: 描述了将虚拟内存页映射到物理内存页的方法。 该方法包括：接收虚拟存储器页面到多个物理存储器页面的映射，检测对包含在多个物理存储器页面中的数据执行的事务的请求，其中事务包括多个数据更新， 多个物理内存页面的数量包含要由事务更新的数据的最新版本，通过在不包含最新版本的多个物理存储器页面中的物理存储器页面内执行事务来更新物理存储器页面 数据，以及更新物理存储器页面中哪一个包含与交易有关的数据的最新版本的指示。