公开(公告)号：US10691344B2

公开(公告)日：2020-06-23

申请号：US14785120

申请日：2013-05-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Doe Hyun Yoon ,  Sheng Li ,  Jichuan Chang ,  Ke Chen ,  Parthasarathy Ranganathan ,  Norman Paul Jouppi

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.

公开(公告)号：US09575542B2

公开(公告)日：2017-02-21

申请号：US13755527

申请日：2013-01-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Doe Hyun Yoon ,  Moray McLaren ,  Dejan S. Milojicic ,  Robert Schreiber ,  Norman Paul Jouppi

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D10/22

Abstract: A power management module can select one of a plurality of different operational modes for a hardware component in a computer system based on application performance and total computer system power consumption determined for each of the operational modes.

Abstract translation: 功率管理模块可以基于针对每个操作模式确定的应用性能和总计算机系统功耗，来选择计算机系统中的硬件组件的多种不同操作模式之一。

公开(公告)号：US10127154B2

公开(公告)日：2018-11-13

申请号：US14764651

申请日：2013-03-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Norman Paul Jouppi ,  Sheng Li ,  Ke Chen

IPC: G06F13/00 ,  G06F12/0844 ,  G06F12/08 ,  G06F12/0811

Abstract: A memory system includes a plurality of memory nodes provided at different hierarchical levels of the memory system, each of the memory nodes including a corresponding memory storage and a cache. A memory node at a first of the different hierarchical levels is coupled to a processor with lower communication latency than a memory node at a second of the different hierarchical levels. The memory nodes are to cooperate to decide which of the memory nodes is to cache data of a given one of the memory nodes.

公开(公告)号：US09846550B2

公开(公告)日：2017-12-19

申请号：US15089730

申请日：2016-04-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Aniruddha Nagendran Udipi ,  Niladrish Chatterjee ,  Rajeev Balasubramonian ,  Alan Lynn Davis ,  Norman Paul Jouppi

IPC: G06F11/10 ,  G06F3/06 ,  G11C5/04 ,  G11C8/12 ,  G11C11/408 ,  G11C7/10 ,  G06F12/0893 ,  G06F12/0802

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0673 ,  G06F11/1088 ,  G06F12/0802 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/3042 ,  G06F2212/305 ,  G11C5/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4082 ,  Y02D10/13

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

公开(公告)号：US10572150B2

公开(公告)日：2020-02-25

申请号：US14784245

申请日：2013-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sheng Li ,  Norman Paul Jouppi ,  Paolo Faraboschi ,  Michael R. Krause

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/38 ,  G06F12/08 ,  G06F11/20 ,  G06F11/34 ,  G06F12/0811

Abstract: According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.

公开(公告)号：US20160216912A1

公开(公告)日：2016-07-28

申请号：US15089730

申请日：2016-04-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Aniruddha Nagendran Udipi ,  Niladrish Chatterjee ,  Rajeev Balasubramonian ,  Alan Lynn Davis ,  Norman Paul Jouppi

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0673 ,  G06F11/1088 ,  G06F12/0802 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/3042 ,  G06F2212/305 ,  G11C5/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4082 ,  Y02D10/13

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition the example apparatus includes a column decoder (606) to selectively activate a portion of the raw based on the column address and the signal asserted on the wordline.

Abstract translation: 所公开的示例性装置包括用于将对应于行（608）的行地址存储在存储器阵列（602）中的行地址寄存器（412）。 示例性装置还包括耦合到行地址寄存器的行解码器（604），用于在存储器接收列地址之后，在行的字线（704）上断言信号。 另外，示例性装置包括列解码器（606），用于基于列地址和在字线上断言的信号选择性地激活原始部分的一部分。