公开(公告)号：US20110175229A1

公开(公告)日：2011-07-21

申请号：US12944876

申请日：2010-11-12

申请人： Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

发明人： Bong-Soo Kim ,  Kwang-Youl Chun ,  Sang-Bin Ahn

IPC分类号： H01L23/522

CPC分类号： H01L23/481 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively.

摘要翻译： 集成电路器件包括在其中具有多个沟槽隔离区域的半导体衬底，其中限定了它们之间的相应的半导体有源区。 沟槽设置在半导体衬底中。 沟槽具有分别限定与第一沟槽隔离区域和第一有源区域相对的界面的第一和第二相对的侧壁。 第一电互连设置在沟槽的底部。 提供了一种电绝缘覆盖图案，其在第一电互连和沟槽的顶部之间延伸。 还提供了互连绝缘层，其将沟槽的第一和第二侧壁和底部排列。 互连绝缘层在第一电互连和第一有源区之间延伸。 在第一活动区域设置有凹部。 凹部具有限定与互连绝缘层的界面的侧壁。 还提供了第二电互连，其延伸在：（i）第一沟槽隔离区的上表面，（ii）电绝缘封盖图案; 和（iii）凹槽的侧壁。 第一和第二电互连分别在第一和第二正交方向跨越半导体衬底延伸。

公开(公告)号：US07781285B2

公开(公告)日：2010-08-24

申请号：US11450936

申请日：2006-06-09

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US07772103B2

公开(公告)日：2010-08-10

申请号：US12146729

申请日：2008-06-26

申请人： Ho-Jun Yi ,  Yong-Il Kim ,  Bong-Soo Kim ,  Dae-Young Jang ,  Woo-Jeong Cho

发明人： Ho-Jun Yi ,  Yong-Il Kim ,  Bong-Soo Kim ,  Dae-Young Jang ,  Woo-Jeong Cho

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/105 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of forming a wire structure, first active regions and second active regions are formed on a substrate. Each of the first active regions has a first sidewall of a positive slope and a second sidewall opposed to the first sidewall. The second active regions are arranged along a first direction. An isolation layer is between the first active regions and the second active regions. A first mask is formed on the first active regions, the second active regions and the isolation layer. The first mask has an opening exposing the first sidewall and extending along the first direction. The first active regions, the second active regions and the isolation layer are etched using the first mask to form a groove extending along the first direction and to form a fence having a height substantially higher than a bottom face of the groove. A wire is formed to fill the groove. A contact is formed on the wire. The contact is disposed toward the second active regions from the fence.

摘要翻译： 在形成线结构的方法中，在衬底上形成第一有源区和第二有源区。 每个第一有源区具有正斜率的第一侧壁和与第一侧壁相对的第二侧壁。 第二有源区沿第一方向排列。 隔离层位于第一有源区和第二有源区之间。 第一掩模形成在第一有源区，第二有源区和隔离层上。 第一掩模具有暴露第一侧壁并沿着第一方向延伸的开口。 使用第一掩模蚀刻第一有源区，第二有源区和隔离层，以形成沿着第一方向延伸的凹槽，并形成具有高于凹槽的底面的高度的栅栏。 形成线以填充凹槽。 在导线上形成接触。 接触件从栅栏朝向第二活动区域设置。

公开(公告)号：US20080061382A1

公开(公告)日：2008-03-13

申请号：US11704364

申请日：2007-02-09

申请人： Seong-Goo Kim ,  Kang-Yoon Lee ,  Yun-Gi Kim ,  Bong-Soo Kim

发明人： Seong-Goo Kim ,  Kang-Yoon Lee ,  Yun-Gi Kim ,  Bong-Soo Kim

IPC分类号： H01L29/768 ,  H01L21/336 ,  H01L21/4763 ,  H01L23/52

CPC分类号： H01L23/485 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

摘要翻译： 提供晶体管，半导体集成电路互连及其形成方法。 晶体管，半导体集成电路互连及其形成方法可以改善栅电极或互连电极之间的电特性，并简化与栅电极或互连电极相关的半导体制造工艺。 可以制备具有第一和第二区域的材料层。 可以在第一区域的选定部分中形成沟槽。 晶体管或半导体集成电路互连可以分别在第一和第二区域中。 晶体管之一或半导体集成电路互连可以形成在沟槽中。 晶体管或半导体集成电路互连可以彼此电绝缘。

公开(公告)号：US20060045542A1

公开(公告)日：2006-03-02

申请号：US10528445

申请日：2003-04-22

申请人： Chang-Hee Lee ,  Kwang-Uk Chu ,  Bong-Soo Kim

发明人： Chang-Hee Lee ,  Kwang-Uk Chu ,  Bong-Soo Kim

IPC分类号： H04B10/04

CPC分类号： H04B10/572

摘要： An optical transmitter has a resonance wavelength characteristic that varies with the refractive index of the optical transmitter. The optical transmitter receives a narrow band injected wavelength signal from an incoherent light source. The controller substantially matches a resonant wavelength of the optical transmitter to the wavelength of the injected wavelength signal by changing the refractive index of the optical transmitter to substantially match the resonant wavelength of the optical transmitter and the wavelength of the injected wavelength signal. A detector measures a parameter of the optical transmitter to provide a feedback signal to a controller to determine when the resonant wavelength of the optical transmitter and the wavelength of the injected wavelength signal are substantially matched.

公开(公告)号：US20160104671A1

公开(公告)日：2016-04-14

申请号：US14970160

申请日：2015-12-15

申请人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

发明人： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC分类号： H01L23/528 ,  H01L23/535 ,  H01L29/06 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

公开(公告)号：US08872262B2

公开(公告)日：2014-10-28

申请号：US12781859

申请日：2010-05-18

申请人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

发明人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

IPC分类号： H01L27/108 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

摘要翻译： 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

公开(公告)号：US20100283094A1

公开(公告)日：2010-11-11

申请号：US12840599

申请日：2010-07-21

申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

公开(公告)号：US07595529B2

公开(公告)日：2009-09-29

申请号：US12176263

申请日：2008-07-18

申请人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

发明人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

IPC分类号： H01L21/768

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices having an upper pattern aligned with a lower pattern molded by a semiconductor substrate and methods of forming the same. In the semiconductor IC devices, the lower pattern contacts the upper pattern using an active region and/or an isolation layer. The methods include preparing a semiconductor substrate having an active region. A lower pattern is formed on the active region. The lower pattern is surrounded by the active region and protrudes from a top surface of the active region. An upper pattern is disposed on the lower pattern. The upper pattern contacts the lower pattern.

摘要翻译： 提供了具有与由半导体衬底模制的下部图案对准的上部图案的半导体集成电路（IC）器件及其形成方法。 在半导体IC器件中，下图案使用有源区和/或隔离层接触上图案。 所述方法包括制备具有活性区域的半导体衬底。 在有源区上形成较低的图案。 下图案被有源区域包围并从有源区域的顶表面突出。 上部图案设置在下部图案上。 上部图案接触下部图案。

公开(公告)号：US20080129466A1

公开(公告)日：2008-06-05

申请号：US11877784

申请日：2007-10-24

申请人： Jae-Hong Ruy ,  Bong-Soo Kim ,  Cheol-Sig Pyo

发明人： Jae-Hong Ruy ,  Bong-Soo Kim ,  Cheol-Sig Pyo

IPC分类号： G08B1/08

CPC分类号： H04W16/14 ,  H04L47/10 ,  Y02D70/166 ,  Y02D70/26

摘要： There is provided a matching system for preventing the loss of data between a low-power network and a non-low-power network, the matching system including: an RF communication schedule management unit, installed in the low-power network side system, for managing a schedule of an RF communication period indicative of a data transmission period of the low-power network; a heterogeneous network communication schedule management unit, disposed in the non-low-power network side system, for creating a schedule to transmit data to the low-power network side system based on the RF communication period provided by the RF communication schedule management unit; and a heterogeneous network communication unit for transmitting the data to the low-power network side system depending on the schedule created by the heterogeneous network communication schedule management unit.

摘要翻译： 提供了一种用于防止低功率网络和非低功率网络之间的数据丢失的匹配系统，所述匹配系统包括：安装在低功率网络侧系统中的RF通信进度管理单元，用于 管理指示低功率网络的数据传输周期的RF通信周期的调度; 设置在非低功率网络侧系统中的异构网络通信调度管理单元，用于基于由RF通信调度管理单元提供的RF通信期间，创建向低功率网络侧系统发送数据的调度; 以及用于根据异构网络通信调度管理单元创建的调度将数据发送到低功率网络侧系统的异构网络通信单元。