公开(公告)号：US08694750B2

公开(公告)日：2014-04-08

申请号：US12339664

申请日：2008-12-19

申请人： Dmitry Vyshetsky ,  Paul Gyugyi

发明人： Dmitry Vyshetsky ,  Paul Gyugyi

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7211

摘要： Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.

摘要翻译： 本发明的实施例涉及一种用于允许在不改变应用固件的情况下在不同性能和成本的存储位置之间移动数据结构的方法和系统。 在一个实施例中，应用固件而不是应用固件直接访问存储器，应用程序固件通过参数来请求数据结构，实现返回指针。 参数可以是例如数据扇区的逻辑块地址，并且数据结构可以是该逻辑块地址（LBA）的映射和关联信息到闪存设备中的位置。

公开(公告)号：US20090150689A1

公开(公告)日：2009-06-11

申请号：US12342865

申请日：2008-12-23

申请人： Brad W. Simeral ,  David C. Reed ,  Dmitry Vyshetsky ,  Roman Surgutchick ,  Robert William Chapman ,  Joshua Titus ,  Anand Srinivasan ,  Hari U. Krishnan

发明人： Brad W. Simeral ,  David C. Reed ,  Dmitry Vyshetsky ,  Roman Surgutchick ,  Robert William Chapman ,  Joshua Titus ,  Anand Srinivasan ,  Hari U. Krishnan

IPC分类号： G06F1/32

CPC分类号： G06F1/28 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component. It also includes a controller for adjusting operational characteristics of the component for modifying the power consumed by the component to comply with a performance profile, which generally specifies permissible power consumption levels for the component.

摘要翻译： 公开了一种数据路径控制器，计算机设备，装置和方法，用于将电源管理功能集成到数据路径控制器中，以管理由处理器和外围设备消耗的功率。 通过在数据路径控制器内部嵌入电源管理，数据路径控制器可以有利地在现场修改其标准，使得其能够根据处理器和外围设备的变化来适应其功率管理动作。 此外，数据路径控制器包括功率管理接口，其提供用于监视和/或量化各种组件的功耗的功率监控端口。 在一个实施例中，数据路径控制器包括用于可选地监视组件的功率的功率监视接口。 它还包括用于调整部件的操作特性的控制器，用于修改部件消耗的功率以符合性能曲线，其通常指定部件的允许功率消耗水平。

公开(公告)号：US06330584B1

公开(公告)日：2001-12-11

申请号：US09055033

申请日：1998-04-03

申请人： Alexander Joffe ,  Dmitry Vyshetsky

发明人： Alexander Joffe ,  Dmitry Vyshetsky

IPC分类号： G06F900

CPC分类号： G06F9/5011 ,  G06F9/3851 ,  G06F9/462 ,  G06F9/4881 ,  G06F2209/507

摘要： In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

摘要翻译： 在多任务流水线处理器中，连续的指令由不同的任务执行，消除了当前一条指令无法完成时清除随后指令的指令执行流水线的需要。 任务不共享存储任务特定值的寄存器，因此在新任务计划执行时不需要保存或加载寄存器。 如果指令访问不可用资源，则指令将被暂停，从而允许执行其他任务的指令，直到资源变为可用。 任务调度由硬件执行; 不需要操作系统。 提供简单的技术来同步不同任务之间的共享资源访问。

公开(公告)号：US07562205B1

公开(公告)日：2009-07-14

申请号：US11844248

申请日：2007-08-23

申请人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

发明人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

IPC分类号： G06F12/00

CPC分类号： G06F12/1036

摘要： A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

摘要翻译： 虚拟地址转换表和片上地址缓存可用于将虚拟地址转换为物理地址。 使用与一些范围的虚拟地址相关联的集群提供地址转换信息，该集群可用于将其范围中的任何虚拟地址转换为物理地址，其中由不同集群映射的范围的大小可能不同。 集群存储在由虚拟地址索引的地址转换表中，以便从任何有效的虚拟地址开始，可以从转换表中检索用于转换该地址的适当集群。 最近检索的群集存储在片上缓存中，并且可以使用高速缓存的群集来翻译其范围内的任何虚拟地址，而不再重新访问地址转换表。

公开(公告)号：US07278008B1

公开(公告)日：2007-10-02

申请号：US10769357

申请日：2004-01-30

申请人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

发明人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

IPC分类号： G06F12/00

CPC分类号： G06F12/1036

摘要： A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

摘要翻译： 虚拟地址转换表和片上地址缓存可用于将虚拟地址转换为物理地址。 使用与一些范围的虚拟地址相关联的集群提供地址转换信息，该集群可用于将其范围中的任何虚拟地址转换为物理地址，其中由不同集群映射的范围的大小可能不同。 集群存储在由虚拟地址索引的地址转换表中，以便从任何有效的虚拟地址开始，可以从转换表中检索用于转换该地址的适当集群。 最近检索的群集存储在片上缓存中，并且可以使用高速缓存的群集来翻译其范围内的任何虚拟地址，而不再重新访问地址转换表。

公开(公告)号：US06307860B1

公开(公告)日：2001-10-23

申请号：US09055044

申请日：1998-04-03

申请人： Alexander Joffe ,  Dmitry Vyshetsky

发明人： Alexander Joffe ,  Dmitry Vyshetsky

IPC分类号： H04L1228

CPC分类号： H04L49/3081 ,  H04L12/5601 ,  H04L49/1553 ,  H04L49/255 ,  H04L49/351 ,  H04L2012/5652 ,  H04L2012/5658 ,  H04L2012/5665 ,  H04Q11/0478

摘要： A processor system suitable to provide an interface between networks includes a software programmable processor and a channel processor that receives data from a network and transforms data at commands from the software programmable processor. The channel can execute only a few simple commands, but these commands are sufficient for a wide range of systems. The commands include (1) a command to transmit received data, perhaps skipping some data; and (2) a command to transmit data specified by the command itself rather than the received data. The channel is fast, simple and inexpensive.

摘要翻译： 适于提供网络之间的接口的处理器系统包括软件可编程处理器和从网络接收数据并以来自软件可编程处理器的命令转换数据的通道处理器。 该通道只能执行几个简单的命令，但这些命令对于广泛的系统是足够的。 命令包括（1）发送接收数据的命令，可能跳过一些数据; 和（2）用于发送由命令本身指定的数据而不是接收到的数据的命令。 频道快速，简单，便宜。

公开(公告)号：US07966439B1

公开(公告)日：2011-06-21

申请号：US10997330

申请日：2004-11-24

申请人： Sean J. Treichler ,  Brad W. Simeral ,  Roman Surgutchick ,  Anand Srinivasan ,  Dmitry Vyshetsky

发明人： Sean J. Treichler ,  Brad W. Simeral ,  Roman Surgutchick ,  Anand Srinivasan ,  Dmitry Vyshetsky

IPC分类号： G06F13/36 ,  G06F3/00 ,  G06F13/12 ,  G06F5/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1689 ,  G06F5/06

摘要： A system controller includes a memory controller and a host interface residing in different clock domains. There is a time delay between the time when the memory controller issues a read command to a memory and the data becoming present and available at the host interface. The memory controller generates an alarm message at or near the time that it issues the read command. The alarm message indicates to the host interface the time that the data is available for transfer to a host.

摘要翻译： 系统控制器包括存储器控制器和驻留在不同时钟域中的主机接口。 在存储器控制器向存储器发出读取命令的时间和数据变得存在并且在主机接口可用之间存在时间延迟。 存储器控制器在发出读取命令的时间或附近产生报警消息。 报警消息向主机接口指示数据可用于传输到主机的时间。

公开(公告)号：US20090282408A1

公开(公告)日：2009-11-12

申请号：US12504313

申请日：2009-07-16

申请人： Alexander Joffe ,  Dmitry Vyshetsky

发明人： Alexander Joffe ,  Dmitry Vyshetsky

IPC分类号： G06F9/46 ,  H04L12/00

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/52 ,  G06F2209/507

摘要： In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

摘要翻译： 在多任务流水线处理器中，连续的指令由不同的任务执行，消除了当前一条指令无法完成时清除随后指令的指令执行流水线的需要。 任务不共享存储任务特定值的寄存器，因此在新任务计划执行时不需要保存或加载寄存器。 如果指令访问不可用资源，则指令将被暂停，从而允许执行其他任务的指令，直到资源变为可用。 任务调度由硬件执行; 不需要操作系统。 提供简单的技术来同步不同任务之间的共享资源访问。

公开(公告)号：US07334108B1

公开(公告)日：2008-02-19

申请号：US10769388

申请日：2004-01-30

申请人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

发明人： Colyn S. Case ,  Dmitry Vyshetsky ,  Sean J. Treichler

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F2212/652 ,  G06F2212/654

摘要： A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

摘要翻译： 虚拟地址转换表和片上地址缓存可用于将虚拟地址转换为物理地址。 使用与一些范围的虚拟地址相关联的集群提供地址转换信息，该集群可用于将其范围中的任何虚拟地址转换为物理地址，其中由不同集群映射的范围的大小可能不同。 集群存储在由虚拟地址索引的地址转换表中，以便从任何有效的虚拟地址开始，可以从转换表中检索用于转换该地址的适当集群。 最近检索的群集存储在片上缓存中，并且可以使用高速缓存的群集来翻译其范围内的任何虚拟地址，而不再重新访问地址转换表。

公开(公告)号：US20060041722A1

公开(公告)日：2006-02-23

申请号：US10920995

申请日：2004-08-17

申请人： Ziyad Hakura ,  Radoslav Danilak ,  Brad Simeral ,  Brian Langendorf ,  Stefano Pescador ,  Dmitry Vyshetsky

发明人： Ziyad Hakura ,  Radoslav Danilak ,  Brad Simeral ,  Brian Langendorf ,  Stefano Pescador ,  Dmitry Vyshetsky

IPC分类号： G06F12/00

CPC分类号： G06F12/0862

摘要： A system, apparatus, and method are disclosed for storing predictions as well as examining and using one or more caches for anticipating accesses to a memory. In one embodiment, an exemplary apparatus is a prefetcher for managing predictive accesses with a memory. The prefetcher can include a speculator to generate a range of predictions, and multiple caches. For example, the prefetcher can include a first cache and a second cache to store predictions. An entry of the first cache is addressable by a first representation of an address from the range of predictions, whereas an entry of the second cache is addressable by a second representation of the address. The first and the second representations are compared in parallel against the stored predictions of either the first cache and the second cache, or both.

摘要翻译： 公开了用于存储预测以及检查和使用一个或多个高速缓存以预测对存储器的访问的系统，装置和方法。 在一个实施例中，示例性装置是用于管理具有存储器的预测访问的预取器。 预取器可以包括一个投机者来生成一系列预测，以及多个高速缓存。 例如，预取器可以包括第一缓存和第二高速缓存来存储预测。 第一高速缓存的条目可由来自预测范围的地址的第一表示来寻址，而第二高速缓存的条目可由地址的第二表示寻址。 将第一和第二表示与第一高速缓存和第二高速缓存或两者的存储的预测并行地进行比较。