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    System for expanded detection and correction of errors in parallel binary data produced by data tracks
    18.
    发明授权
    System for expanded detection and correction of errors in parallel binary data produced by data tracks 失效
    数据跟踪产生的并行二进制数据中扩展检测和纠正错误的系统

    公开(公告)号：US3675200A

    公开(公告)日：1972-07-04

    申请号：US3675200D

    申请日：1970-11-23

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS C ,  HENLE ROBERT A ,  HSIAO MU Y ,  MALEY GERALD A ,  PRICER W DAVID

    IPC: G06F11/10 ,  G11C29/00 ,  G06F11/08 ,  G06K5/00

    CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C29/003

    Abstract: Errors in parallel binary data produced by a plurality of data track, e.g., a plurality of parallel shift registers, are corrected by a system in which the shift registers which are stuck, i.e., inalterable, are determined and counted. By single Hamming error detection means, the presence of a Hamming error and an indication of the bit position of a single Hamming error is made. Comparison means determine if the indicated Hamming error is coincident with a stuck track. Then, dependent on the parity condition of the data as well as the count of stuck tracks, apparatus is provided for complementing one or more of the stuck tracks and/or correcting the indicated Hamming error.

    Abstract translation: 由多个数据磁道（例如多个并行移位寄存器）产生的并行二进制数据的错误由其中确定并计数被卡住的，即不可更改的移位寄存器的系统来校正。 通过单个汉明误差检测装置，进行汉明误差的存在和单个汉明误差的比特位置的指示。 比较装置确定所指示的汉明误差是否与卡盘轨迹一致。 然后，依赖于数据的奇偶校验条件以及卡盘轨迹的计数，提供装置用于补充一个或多个卡住轨迹和/或校正所指示的汉明误差。

    Means for reducing power consumption in a memory device
    19.
    发明授权
    Means for reducing power consumption in a memory device 失效
    用于降低存储器件中的功耗的手段

    公开(公告)号：US3599182A

    公开(公告)日：1971-08-10

    申请号：US3599182D

    申请日：1969-01-15

    Applicant: IBM

    Inventor： HENLE ROBERT A

    IPC: G11C8/00 ,  G11C8/10 ,  G11C11/414 ,  H03M7/00 ,  G11C7/00 ,  G11C5/02

    CPC classification number: G11C11/414 ,  G11C8/10 ,  H03M7/00

    Abstract: The decoding means, which is utilized to select a storage cell or word in a memory device, is divided into a main decoder and at least a first group of decoders whereby only one of the first group of the decoders is activated when the main decoder is energized. Each of the decoders of the first group may be divided into a plurality of decoders that form a second group so that only one of the decoders of the second group also needs to be activated when the decoder of the first group is energized.

    Pulse power data storage cell
    20.
    发明授权
    Pulse power data storage cell 失效
    脉冲电源数据存储单元

    公开(公告)号：US3564300A

    公开(公告)日：1971-02-16

    申请号：US3564300D

    申请日：1968-03-06

    Applicant: IBM

    Inventor： HENLE ROBERT A

    IPC: G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  H03K3/012 ,  H03K3/356 ,  H03K3/26

    CPC classification number: G11C11/414 ,  G11C11/4026 ,  G11C11/4113 ,  G11C11/4116 ,  H03K3/012 ,  H03K3/356

    Abstract: A semiconductor storage cell for use in monolithic memories that perform storage and/or logic and storage functions. These cells each comprise a pair of semiconductor devices which are coupled together to form a bistable circuit. The bistable circuit is intermittently connected to a power supply in such a manner that the internal storage charge characteristics of the monolithic cell present a high-impedance discharge path when the power supply is in an off state. When the power supply is turned on the remaining voltage on the storage charge circuit is sufficient to insure that the monolithic memory cell attains its previous bistable state which existed prior to the power supply being turned off.

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