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    Ternary latches
    11.
    发明授权
    Ternary latches 失效
    三月

    公开(公告)号：US3671763A

    公开(公告)日：1972-06-20

    申请号：US3671763D

    申请日：1971-02-05

    Applicant: IBM

    Inventor： MALEY GERALD A ,  WALSH JAMES L

    IPC: H03K3/29 ,  H03K19/08

    CPC classification number: H03K3/29

    Abstract: Two latch circuits are disclosed for three-state operation in the ternary mode. The set input may be raised to a 1 or intermediate voltage level thereby providing a 1 level at the output which remains latched at that level after the set input is lowered to the 0 or lowermost level. When the set input is raised to the uppermost or 2 level the output is set at the 2 level and remains latched at that level when the set input is lowered to the 0 level. The circuits are reset to 0 by raising the reset input to the 2 level.

    Abstract translation: 公开了两种锁存电路，用于三态模式下的三态操作。 所设置的输入可以升高到1或中间电压电平，从而在输出端提供1电平，该电平在设定输入降低到0或最低电平之后保持锁存在该电平。 当设定输入升至最高或2级时，输出设置为2级，当设定输入降低到0电平时，保持锁存在该电平。 通过将复位输入提高到2电平将电路复位为0。

    Three state latch
    16.
    发明授权
    Three state latch 失效
    三态闩锁

    公开(公告)号：US3909634A

    公开(公告)日：1975-09-30

    申请号：US11300171

    申请日：1971-02-05

    Applicant: IBM

    Inventor： MALEY GERALD A ,  WALSH JAMES L

    IPC: H03K3/29

    CPC classification number: H03K3/29

    Abstract: A ternary latch circuit has an input set line, an output line, and a reset line. The potential of the output line follows that of the input set line as the potential of the latter is raised from the 0 state through the 1 state to the 2 state. The output line potential is held at the highest level reached by the set line. When the reset line is raised, the potential of the output line falls to its original value.

    Abstract translation: 三进制锁存电路具有输入设置线，输出线和复位线。 输出线的电位遵循输入设定线的电位，因为后者的电位从0状态升高到1状态到2状态。 输出线电位保持在设定线达到的最高水平。 当复位线上升时，输出线的电位下降到原来的值。

    Basic ternary logic circuits
    17.
    发明授权
    Basic ternary logic circuits 失效
    基本逻辑电路

    公开(公告)号：US3660678A

    公开(公告)日：1972-05-02

    申请号：US3660678D

    申请日：1971-02-05

    Applicant: IBM

    Inventor： MALEY GERALD A ,  WALSH JAMES L

    IPC: H03K19/082 ,  H03K19/08 ,  H03K19/40

    CPC classification number: H03K19/0823

    Abstract: Basic ternary logic circuits provide all 27 single-variable ternary logic functions. Each of two current switches comprises a pair of transistors. Each transistor has an emitter connected to a respective one of a pair of current sources. The collector of one transistor of each current switch is connected to a load impedance and the collector of the other transistor is connected to a power supply. The input is at the base of one of the current switch transistors. The signal at the junction of the load impedance and the collectors is transmitted to the output by an emitter follower.

    Abstract translation: 基本三元逻辑电路提供所有27个单变量三元逻辑功能。 两个电流开关中的每一个包括一对晶体管。 每个晶体管具有连接到一对电流源中的相应一个的发射极。 每个电流开关的一个晶体管的集电极连接到负载阻抗，另一个晶体管的集电极连接到电源。 输入端是一个电流开关晶体管的基极。 负载阻抗和集电极的结点处的信号通过射极跟随器传输到输出端。

    Interchanger 1 circuits
    18.
    发明授权
    Interchanger 1 circuits 失效
    交换机1电路

    公开(公告)号：US3660677A

    公开(公告)日：1972-05-02

    申请号：US3660677D

    申请日：1971-02-05

    Applicant: IBM

    Inventor： MALEY GERALD A ,  WALSH JAMES L

    IPC: H03K19/082 ,  H03K19/08 ,  H03K19/40

    CPC classification number: H03K19/0823

    Abstract: A ternary logic circuit provides the Interchanger 1 logic function whereby for an input of levels 0, 1 or 2 there arises an output with levels 2, 1 or 0, respectively. A transistor current switch has two current paths only one of which includes a load impedance, the other current path bypassing the load impedance. A current source provides two units of current. Either none, one or both of the current units flow in the load impedance to provide the respective output levels, depending upon the input signal.

    Abstract translation: 三元逻辑电路提供交换器1的逻辑功能，由此对于0,1或2级的输入，分别产生具有级别2，1或0的输出。 晶体管电流开关具有两个电流路径，其中仅一个包括负载阻抗，另一个电流路径绕过负载阻抗。 电流源提供两个电流单位。 当前单元中的一个或两个都流入负载阻抗，以根据输入信号提供相应的输出电平。

    Random number statistical logic test system
    19.
    发明授权
    Random number statistical logic test system 失效
    随机数统计逻辑测试系统

    公开(公告)号：US3614608A

    公开(公告)日：1971-10-19

    申请号：US3614608D

    申请日：1969-05-19

    Applicant: IBM

    Inventor： GIEDD GARY R ,  MALEY GERALD A ,  PERKINS MERLYN H

    IPC: G06F11/22 ,  G01R31/3183 ,  G01R31/3193 ,  G06F7/58 ,  H03K3/84 ,  G01R15/12

    CPC classification number: G01R31/3193 ,  G01R31/318385

    Abstract: A system for testing complex circuitry primarily in large scale integration, where a great number of inputs and outputs must be tested and the internal circuitry is inaccessible. The test system has a random number generator which simultaneously applies a plurality of signals in a random pattern to the plurality of input pins of both the test circuit and a reference circuit. Compare circuitry is responsive to signals received from the test and reference circuits and provides an error signal when the two outputs are not matched.

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