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56 条记录 (耗时 0.012 秒)

    Circuit arrangement for frequency division
    1.
    发明授权
    Circuit arrangement for frequency division 失效
    分频电路布置

    公开(公告)号：US4242601A

    公开(公告)日：1980-12-30

    申请号：US953680

    申请日：1978-10-23

    申请人： Wolfdietrich G. Kasperkovitz

    发明人： Wolfdietrich G. Kasperkovitz

    IPC分类号： H03B19/00 ,  H03B19/14 ,  H03K3/29 ,  H03K21/00 ,  H03K23/52 ,  H03K23/00 ,  H03K27/00

    CPC分类号： H03K3/29 ,  H03B19/14

    摘要： A wide-band frequency divider having a first and a second group of n transistors each, with their emitters in a first cyclic sequence alternately connected to the collectors of two transistors forming an input differential pair. The base electrode of any arbitrary transistor of said first cyclic sequence is always connected to the collector of the (n-1).sup.th transistor after said arbitrary transistor in said first sequence. The frequency divider further comprises a third and a fourth group of n transistors each, also with their emitters alternatley connected in a second cyclic sequence to the collectors of two transistors which constitute an input differential pair. The collectors of the transistors in the second sequence are each time connected to the collector of the next transistor in the first sequence. The base electrode of any arbitrary transistor of said second cyclic sequence is always connected to the collector of the n.sup.th transistor after said arbitrary transistor in that sequence.

    摘要翻译： 宽带分频器，其具有第一和第二组n个晶体管，其发射器以第一循环序列交替地连接到形成输入差分对的两个晶体管的集电极。 所述第一循环序列的任意晶体管的基极在所述第一序列中的所述任意晶体管之后总是连接到第（n-1）晶体管的集电极。 分频器还包括第三和第四组n个晶体管，每个n个晶体管的发射极也以第二循环序列连接到构成输入差分对的两个晶体管的集电极。 第二个序列中的晶体管的集电极在第一个序列中每个时间连接到下一个晶体管的集电极。 所述第二循环序列的任意晶体管的基极在该序列中在所述任意晶体管之后总是连接到第n晶体管的集电极。

    Tri-state logic circuit
    2.
    发明授权
    Tri-state logic circuit 失效
    三态逻辑电路

    公开(公告)号：US4029971A

    公开(公告)日：1977-06-14

    申请号：US657838

    申请日：1976-02-13

    申请人： Richard Lee Pryor

    发明人： Richard Lee Pryor

    IPC分类号： H03K3/29 ,  H03K17/687 ,  H03K19/094 ,  H03K1/00 ,  H03K19/08

    CPC分类号： H03K3/29 ,  H03K17/6872 ,  H03K19/09429

    摘要： A line driver including a pair of complementary transistors having their conduction paths serially connected between an operating and a reference potential and their bases connected through a first switch to a signal input terminal. A second switch is connected between the common base connection and the common connection of the conduction paths. With the second switch open and the first closed, an output voltage, responsive to the input signal, corresponding to first or second binary values is obtained. When the second switch is closed and the first opened, the transistor pair is turned off, disconnecting the line driver from its load, thereby providing tri-state logic operation.

    摘要翻译： 一种线驱动器，包括一对互补晶体管，其导通路径串联连接在工作电压和参考电位之间，其基极通过第一开关连接到信号输入端。 第二开关连接在公共基座连接和传导路径的公共连接之间。 当第二开关断开并且第一闭合时，获得对应于第一或第二二进制值的响应于输入信号的输出电压。 当第二开关闭合并且首先断开时，晶体管对被关断，从而使线驱动器与其负载断开，由此提供三态逻辑运算。

    Multistable circuit arrangement
    3.
    发明授权
    Multistable circuit arrangement 失效
    多路电路布置

    公开(公告)号：US3860834A

    公开(公告)日：1975-01-14

    申请号：US37919373

    申请日：1973-07-13

    申请人： STUTZ THEO ,  MULLER ALBERT

    发明人： STUTZ THEO ,  MULLER ALBERT

    IPC分类号： H03K3/29 ,  H03K17/965 ,  H03K17/98 ,  H03M11/00

    CPC分类号： H03K17/965 ,  H03K3/29 ,  H03K17/98 ,  H03M11/00

    摘要： A multistable circuit arrangement comprising a multiplicity n of at least three storage stages each of the storage stages possessing two possible operating states each of the n storage stages comprising amplifier stages, each amplifier stage having control inputs and at least one output, a variable coupling impedance operatively associated with each amplifier stage, wherein for each operating state of the circuit arrangement a random one of the n amplifier stages assumes one of both possible operating states whereas all of the other amplifier stages assume the other operating state, until upon actuating a given one of the coupling impedances of the amplifier stages operating in the other operating state the aforesaid one operating state becomes instable and only the other operating state is possible, so that only the amplifier stage associated with the actuated coupling impedance is positively controlled to assume said one operating state and to remain therein.

    摘要翻译： 一种多电路电路装置，包括至少三个存储级的多个n个存储级，每个存储级具有两个可能的操作状态，每个n个存储级包括放大器级，每个放大器级具有控制输入和至少一个输出，可变耦合阻抗 可操作地与每个放大器级相关联，其中对于电路装置的每个操作状态，n个放大器级中的随机的一个放在两个可能的操作状态之中，而所有其他放大器级都采用另一个操作状态，直到启动给定的一个 在另一个操作状态下工作的放大器级的耦合阻抗是上述的一个操作状态变得不稳定，并且只有另一个操作状态是可能的，使得只有与被激励的耦合阻抗相关联的放大器级被正确地控制以承担所述一个操作 状态并留在其中。

    Low-power high-frequency divider
    4.
    发明授权
    Low-power high-frequency divider 失效
    低功耗高频分频器

    公开(公告)号：US3619643A

    公开(公告)日：1971-11-09

    申请号：US3619643D

    申请日：1970-06-11

    申请人： MOTOROLA INC

    发明人： DAVIS WILLIAM FOLSOM

    IPC分类号： H03B19/14 ,  H03K3/29 ,  H03K23/08

    CPC分类号： H03B19/14 ,  H03K3/29

    摘要： A frequency divider is disclosed in which six transistors are connected in three pairs, the collector of the second one of each pair of transistors is connected to the collector of the first transistor of another pair of transistors providing a ringlike configuration, while the collector of the first one of each pair is coupled via a capacitor to the base of the other one of that pair of transistors and the current through the emitters of each of the pairs is supplied from a constant current source. The resultant frequency divider when using good high-frequency lowcurrent transistors requires power in the order of one-seventieth of the power required by known similar frequency dividers.

    Solid state switching and memory apparatus
    5.
    发明授权
    Solid state switching and memory apparatus 失效
    固态开关和存储器

    公开(公告)号：US3562721A

    公开(公告)日：1971-02-09

    申请号：US3562721D

    申请日：1963-03-05

    申请人： FAIRCHILD CAMERA INSTR CO

    发明人： NORMAN ROBERT H

    IPC分类号： G11C11/411 ,  H01L29/08 ,  H03K3/286 ,  H03K3/288 ,  H03K3/29 ,  G11C11/40 ,  H03K3/281

    CPC分类号： H03K3/288 ,  G11C11/4116 ,  H01L29/0813 ,  H03K3/286 ,  H03K3/29

    摘要： PARALLEL CONNECTED TRANSISTORS ARE USED IN AN INTEGRATED CIRCUIT ARRAY TO PROVIDE A SWITCHING AND MEMORY FUNCTION. THIS INVENTION RELATES TO A SEMICONDUCTOR SWITCHING CIRCUIT AND MEMORY APPARATUS. MORE SPECIFICALLY, THE INVENTION IS A SWITCHING CIRCUIT WHICH REQUIRES TWO INDEPENDENT PULSES TO CHANGE STATE, AND A HIGH-SPEED DATA STORAGE SYSTEM USING THIS SWITCHING CIRCUIT.

    摘要翻译： 具有两个晶体管的存储单元，每个晶体管具有两个发射极，一个基极和一个集电极; 晶体管的基极和集电极交叉耦合; 通过将第一信号同时施加到两个晶体管中的每一个的发射极之一，同时将第二信号同时施加到两个晶体管中仅一个晶体管的另一个发射极，在其发射极处具有第二信号的晶体管是 放置在导通状态，使得数据被存储在具有致动发射器的单元中。

    Auto-reset ternary latch
    9.
    发明授权
    Auto-reset ternary latch 失效
    自动复位三重锁

    公开(公告)号：US3671764A

    公开(公告)日：1972-06-20

    申请号：US3671764D

    申请日：1971-02-05

    申请人： IBM

    发明人： MALEY GERALD A ,  WALSH JAMES L

    IPC分类号： H03K3/29 ,  H03K19/00 ,  H03K3/14

    CPC分类号： H03K3/29

    摘要： An auto-reset ternary latch has a data input line, a gate line and an output line. Each of said lines is adapted to assume any one of three potential levels. When the potential of the gate is lowered from the uppermost level to an intermediate level, the potential of the output line moves up or down one level to an intermediate value. When the potential of the gate is lowered all the way to the lowermost level, the potential of the output line matches that of the data input line. The potential of the output line is maintained at said value when the potential of the gate line is thereafter raised.

    摘要翻译： 自动复位三进制锁存器具有数据输入线，栅极线和输出线。 所述线中的每一条适于承担三个电位电平中的任何一个。 当门的电位从最高电平降低到中间电平时，输出线的电位向上或向下移动一级到中间值。 当门的电位一直下降到最低电平时，输出线的电位与数据输入线的电位相匹配。 当栅极线的电位此后升高时，输出线的电位保持在所述值。