中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.029 seconds)

    Auto-reset ternary latch
    1.
    发明授权
    Auto-reset ternary latch 失效
    自动复位三重锁

    公开(公告)号：US3671764A

    公开(公告)日：1972-06-20

    申请号：US3671764D

    申请日：1971-02-05

    Applicant: IBM

    Inventor： MALEY GERALD A ,  WALSH JAMES L

    IPC: H03K3/29 ,  H03K19/00 ,  H03K3/14

    CPC classification number: H03K3/29

    Abstract: An auto-reset ternary latch has a data input line, a gate line and an output line. Each of said lines is adapted to assume any one of three potential levels. When the potential of the gate is lowered from the uppermost level to an intermediate level, the potential of the output line moves up or down one level to an intermediate value. When the potential of the gate is lowered all the way to the lowermost level, the potential of the output line matches that of the data input line. The potential of the output line is maintained at said value when the potential of the gate line is thereafter raised.

    Abstract translation: 自动复位三进制锁存器具有数据输入线，栅极线和输出线。 所述线中的每一条适于承担三个电位电平中的任何一个。 当门的电位从最高电平降低到中间电平时，输出线的电位向上或向下移动一级到中间值。 当门的电位一直下降到最低电平时，输出线的电位与数据输入线的电位相匹配。 当栅极线的电位此后升高时，输出线的电位保持在所述值。

    Ternary read-only memory
    7.
    发明授权
    Ternary read-only memory 失效
    第三版只读存储器

    公开(公告)号：US3656117A

    公开(公告)日：1972-04-11

    申请号：US3656117D

    申请日：1971-02-05

    Applicant: IBM

    Inventor： MALEY GERALD A ,  WALSH JAMES L

    IPC: G11C11/56 ,  G11C17/08 ,  G11C17/00 ,  G11C11/40

    CPC classification number: G11C11/5692 ,  G11C11/56 ,  G11C17/08

    Abstract: A ternary read-only memory comprises a matrix of transistors arranged in rows and columns. A plurality of bit lines are each connected to the transistors of a respective one of the columns. Connected to the emitter of each transistor is an impedance which may be either a diode, a conductive shunt or an open circuit. A word amplifier is connected to each row of transistors. Means are provided for energizing one of the bit lines and one of the word amplifiers so as to select one transistor for reading out. Each word amplifier includes means for generating a ternary logic function depending upon the value of the impedance connected to the emitter of the transistor selected by energization of the respective bit line and word amplifiers.

    Abstract translation: 三进制只读存储器包括以行和列排列的晶体管矩阵。 多个位线各自连接到相应一个列的晶体管。 连接到每个晶体管的发射极是阻抗，其可以是二极管，导电分路或开路。 字放大器连接到每行晶体管。 提供了用于激励位线之一和一个字放大器以便选择一个用于读出的晶体管的装置。 每个字放大器包括用于根据连接到通过相应位线和字放大器通电选择的晶体管的发射极的阻抗的值产生三元逻辑功能的装置。

Patent Agency Ranking