公开(公告)号：US11276430B2

公开(公告)日：2022-03-15

申请号：US17116895

申请日：2020-12-09

Applicant: IMEC vzw

Inventor： Stefan Cosemans

IPC: G11B15/26 ,  G11B5/008 ,  G11B15/60

Abstract: A storage device including a tape configured to store data is disclosed. The tape includes a plurality of first regions with a first dielectric constant and a plurality of second regions with a second dielectric constant that is higher than the first dielectric constant. The first regions and the second regions are arranged in an alternating manner along the length of the tape. Further, the storage device includes one or more actuators configured to apply an electrical field across the width of the tape, in order to move the tape in length direction. Further, the storage device includes one or more data heads configured to read and/or write data from and/or to the tape.

公开(公告)号：US20210310981A1

公开(公告)日：2021-10-07

申请号：US17208080

申请日：2021-03-22

Applicant: IMEC VZW

Inventor： Olivier Henry ,  Arnaud Furnemont ,  Stefan Cosemans

IPC: G01N27/327 ,  B82Y30/00 ,  G11C11/408

Abstract: In a first aspect, the present disclosure relates to a system for addressing nanoelectrodes in a nanoelectrode array, the system including an array of electrode cells, each electrode cell including: an access transistor having a gate resistively coupled to a word line, a source resistively coupled to a bit line, and a drain, and a storage circuit resistively coupled to the drain and including a nanoelectrode.

公开(公告)号：US11342261B2

公开(公告)日：2022-05-24

申请号：US16721277

申请日：2019-12-19

Applicant: IMEC VZW

Inventor： Stefan Cosemans ,  Julien Ryckaert ,  Zsolt Tokei

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend.

公开(公告)号：US10043798B2

公开(公告)日：2018-08-07

申请号：US15247127

申请日：2016-08-25

Applicant: IMEC VZW

Inventor： Stefan Cosemans ,  Praveen Raghavan ,  Steven Demuynck ,  Julien Ryckaert

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L21/74 ,  H01L29/78

Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.

公开(公告)号：US09224448B2

公开(公告)日：2015-12-29

申请号：US14558523

申请日：2014-12-02

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Stefan Cosemans ,  Ann Witvrouw ,  Maliheh Ramezani

IPC: G11C11/00 ,  G11C11/40 ,  G11C11/50 ,  G11C11/52 ,  G11C23/00 ,  G11C5/06

CPC classification number: G11C11/40 ,  G11C5/06 ,  G11C11/50 ,  G11C11/52 ,  G11C23/00

Abstract: A non-volatile memory arrangement comprising a plurality of cells is disclosed. In one aspect, each cell comprises a memory element and a read selector in series. Further, the memory element is a nano-electro-mechanical switch comprising an anchor, a beam fixed to the anchor, a first and second control gate, for controlling the position of the beam, a first output node against which the beam can be positioned. The cell also comprises a read selector comprising a first selector terminal, a second selector terminal, the first selector terminal connected to the first output node. The first respectively second control gates of switches of a same word are connected together by a first respectively second write word line serving as control gate.

Abstract translation: 公开了包括多个单元的非易失性存储器装置。 在一个方面，每个单元包括串联的存储元件和读选择器。 此外，存储元件是纳米机电开关，其包括锚固件，固定到锚固器的梁，用于控制梁的位置的第一和第二控制栅极，梁可以定位的第一输出节点 。 单元还包括读选择器，包括第一选择器端子，第二选择器端子，连接到第一输出节点的第一选择器端子。 相同字的开关的第一个第二控制栅极通过用作控制栅极的第一分别为第二写入字线连接在一起。

公开(公告)号：US20150179278A1

公开(公告)日：2015-06-25

申请号：US14558505

申请日：2014-12-02

Applicant: IMEC vzw

Inventor： Stefan Cosemans

IPC: G11C23/00

CPC classification number: G11C23/00 ,  G11C11/54 ,  H01H1/0094

Abstract: A data storage cell for storing data is disclosed. In one aspect, the data storage cell comprises a first nano electromechanical switch comprising a first moveable beam fixed to a first anchor, a first control gate and a second control gate, a first output node against which the first moveable beam can be positioned. The data storage cell also comprises a second nano electromechanical switch comprising a second moveable beam fixed to a second anchor, a third control gate and a fourth control gate. The second moveable beam can be positioned against the first output node. Further, the first nano electromechanical switch and the second nano electromechanical switch are configured for selecting a first or a second state of the data storage cell and are configured for having their moveable beam complementary positioned to the first output node. A memory arrangement of such data storage cells is also disclosed, as well as methods for writing data to the data storage cells and for reading data from the data storage cells.

Abstract translation: 公开了一种用于存储数据的数据存储单元。 在一个方面，数据存储单元包括第一纳米机电开关，其包括固定到第一锚定器的第一可移动梁，第一控制栅极和第二控制栅极，第一可移动梁可定位在第一输出节点上。 数据存储单元还包括第二纳米机电开关，其包括固定到第二锚定器，第三控制栅极和第四控制栅极的第二可移动光束。 第二可移动梁可以抵靠第一输出节点定位。 此外，第一纳米机电开关和第二纳米机电开关被配置为选择数据存储单元的第一或第二状态，并且被配置为使其可移动波束互补地定位到第一输出节点。 还公开了这种数据存储单元的存储器布置，以及用于将数据写入数据存储单元并从数据存储单元读取数据的方法。