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    Area-Selective Deposition of a Mask Material
    11.
    发明申请
    Area-Selective Deposition of a Mask Material 审中-公开

    公开(公告)号：US20190355619A1

    公开(公告)日：2019-11-21

    申请号：US16412923

    申请日：2019-05-15

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez

    IPC: H01L21/768 ,  H01L21/311

    Abstract: A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSix selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSix.

    Methods of semiconductor device processing
    13.
    发明授权
    Methods of semiconductor device processing 有权

    公开(公告)号：US11527431B2

    公开(公告)日：2022-12-13

    申请号：US17119802

    申请日：2020-12-11

    Applicant: IMEC vzw

    Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Geert Mannaert

    IPC: H01L21/762 ,  H01L21/8234

    Abstract: According to an aspect of the disclosed technology, there is provided a method comprising: providing a substrate, the substrate supporting an STI-layer and a set of fin structures, each fin structure comprising an upper portion protruding above the STI-layer, forming a spacer layer over the upper portions of the set of fin structures and the STI-layer, forming a sacrificial layer over the spacer layer, the sacrificial layer at least partially embedding the upper portions of the fin structures, partially etching back the sacrificial layer to expose spacer layer portions above upper surfaces of the upper portions of the set of fin structures, and etching the spacer layer and exposing at least the upper surfaces of the upper portions of the set of fin structures, while the sacrificial layer at least partially masks spacer layer portions above the STI-layer.

    Method of forming a mask layer
    14.
    发明授权
    Method of forming a mask layer 有权

    公开(公告)号：US11430697B2

    公开(公告)日：2022-08-30

    申请号：US16843706

    申请日：2020-04-08

    Applicant: IMEC vzw

    Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez

    IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66 ,  H01L21/033

    Abstract: A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.

    Method for Producing a Pillar Structure in a Semiconductor Layer
    16.
    发明申请
    Method for Producing a Pillar Structure in a Semiconductor Layer 审中-公开

    公开(公告)号：US20170103889A1

    公开(公告)日：2017-04-13

    申请号：US15258838

    申请日：2016-09-07

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Vasile Paraschiv ,  Efrain Altamirano Sanchez ,  Zheng Tao

    IPC: H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308

    Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

    Method for Dopant Implantation of FinFET Structures
    17.
    发明申请
    Method for Dopant Implantation of FinFET Structures 审中-公开
    FinFET结构的掺杂剂注入方法

    公开(公告)号：US20150064889A1

    公开(公告)日：2015-03-05

    申请号：US14470462

    申请日：2014-08-27

    Applicant: IMEC VZW

    Inventor： Vasile Paraschiv ,  Gustaf Winroth ,  Efrain Altamirano Sanchez ,  Sabrina Locorotondo ,  Raja Athimulam

    IPC: H01L21/027 ,  H01L21/033 ,  H01L21/266

    CPC classification number: H01L21/0276 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821

    Abstract: The present disclosure is related to a method for implanting dopant elements in a structure comprising a plurality of semiconductor fins separated by field dielectric areas. The method includes depositing an etch stop layer on the fins, depositing a BARC layer on the etch stop layer, depositing a resist layer on the BARC layer, removing a portion of the resist layer by lithography steps to thereby expose an area of the BARC layer, removing the BARC layer in the exposed area by a dry etch process using the remaining resist layer as a mask, implanting dopant elements into the fins present in the area, using the BARC and resist layers as a mask, and removing the remainder of the resist and BARC layers.

    Abstract translation: 本公开涉及用于在包括由场介电区域分离的多个半导体鳍片的结构中注入掺杂剂元素的方法。 该方法包括在鳍片上沉积蚀刻停止层，在蚀刻停止层上沉积BARC层，在BARC层上沉积抗蚀剂层，通过光刻步骤去除抗蚀剂层的一部分，从而暴露BARC层的一个区域 通过使用剩余的抗蚀剂层作为掩模的干蚀刻工艺去除曝光区域中的BARC层，使用BARC和抗蚀剂层作为掩模将掺杂剂元素注入到存在于该区域中的散热片中，并且除去其余的 抗蚀剂和BARC层。

    Method for producing self-aligned gate and source/drain via connections for contacting a FET transistor
    20.
    发明授权
    Method for producing self-aligned gate and source/drain via connections for contacting a FET transistor 有权

    公开(公告)号：US11430876B2

    公开(公告)日：2022-08-30

    申请号：US17083125

    申请日：2020-10-28

    Applicant: IMEC vzw

    Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

    IPC: H01L29/66 ,  H01L21/768

    Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

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