公开(公告)号：US20190198638A1

公开(公告)日：2019-06-27

申请号：US16216833

申请日：2018-12-11

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Hanns Christoph Adelmann ,  Han Chung Lin

IPC: H01L29/66 ,  H01L21/02

Abstract: The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

公开(公告)号：US20180102365A1

公开(公告)日：2018-04-12

申请号：US15729532

申请日：2017-10-10

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Julien Ryckaert ,  Hyungrock Oh

IPC: H01L27/108 ,  H01L21/8254 ,  G11C11/405

CPC classification number: H01L27/108 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01L21/8254 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/10805 ,  H01L28/60

Abstract: The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.

公开(公告)号：US20170178712A1

公开(公告)日：2017-06-22

申请号：US15385593

申请日：2016-12-20

Applicant: IMEC VZW

Inventor： Jan Van Houdt

IPC: G11C11/22 ,  H01L27/1159

CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C16/0475 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

Abstract: The disclosed technology relates generally to non-volatile memory devices, and more particularly to ferroelectric non-volatile memory devices. In one aspect, a non-volatile memory cell includes a pinch-off ferroelectric memory FET and at least one select device electrically connected in series to the pinch-off ferroelectric memory FET.

公开(公告)号：US12041782B2

公开(公告)日：2024-07-16

申请号：US17817550

申请日：2022-08-04

Applicant: IMEC VZW

Inventor： Jan Van Houdt

IPC: H10B51/30 ,  G11C11/22 ,  H10B51/20

CPC classification number: H10B51/30 ,  G11C11/223 ,  G11C11/2275 ,  H10B51/20

Abstract: The present disclosure relates to memory devices, in particular, flash memory devices, storage class memory (SCM) devices or dynamic random access memory (DRAM) devices. The disclosure provides a memory device with a ferroelectric trapping layer. In particular, a memory cell for the memory device comprises a layer stack including: a semiconductor layer; a tunnel layer provided directly on the semiconductor layer; a ferroelectric trapping layer provided directly on the tunnel layer; and a conductive gate layer provided directly on the ferroelectric trapping layer. A blocking layer between the ferroelectric trapping layer and the gate layer may be omitted.

公开(公告)号：US20230262990A1

公开(公告)日：2023-08-17

申请号：US17817550

申请日：2022-08-04

Applicant: IMEC VZW

Inventor： Jan Van Houdt

IPC: H10B51/30 ,  H10B51/20 ,  G11C11/22

CPC classification number: H10B51/30 ,  H10B51/20 ,  G11C11/223 ,  G11C11/2275

Abstract: The present disclosure relates to memory devices, in particular, flash memory devices, storage class memory (SCM) devices or dynamic random access memory (DRAM) devices. The disclosure provides a memory device with a ferroelectric trapping layer. In particular, a memory cell for the memory device comprises a layer stack including: a semiconductor layer; a tunnel layer provided directly on the semiconductor layer; a ferroelectric trapping layer provided directly on the tunnel layer; and a conductive gate layer provided directly on the ferroelectric trapping layer. A blocking layer between the ferroelectric trapping layer and the gate layer may be omitted.

公开(公告)号：US20220328510A1

公开(公告)日：2022-10-13

申请号：US17714895

申请日：2022-04-06

Applicant: IMEC vzw

Inventor： Jan Van Houdt

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78

Abstract: The disclosed technology generally relates to memory structures, for example for a vertical NAND memory. In one aspect, a memory structure includes a substrate and a layer stack arranged on a surface of the substrate, wherein the layer stack includes one or more conductive material layers alternating with one or more dielectric material layers. The memory structure can also include a trench in the layer stack, wherein the trench is formed through the one or more conductive material layers, and wherein the trench includes inner side walls. The memory structure also includes a programmable material layer arranged in the trench and which covers the inner side walls of the trench. The memory structure further includes an oxide semiconductor layer arranged in the trench over the programmable material layer.

公开(公告)号：US20200006380A1

公开(公告)日：2020-01-02

申请号：US16563114

申请日：2019-09-06

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/24 ,  H01L29/10 ,  H01L29/66 ,  H01L45/00

Abstract: The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a vertical three-dimensional semiconductor memory device comprises a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell. The semiconductor memory device additionally includes at least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material.

公开(公告)号：US20190206474A1

公开(公告)日：2019-07-04

申请号：US16226356

申请日：2018-12-19

Applicant: IMEC vzw

Inventor： Jan Van Houdt

IPC: G11C11/22 ,  H01L23/528 ,  H01L27/11507

CPC classification number: G11C11/221 ,  G11C11/22 ,  G11C11/2273 ,  G11C11/2275

Abstract: The disclosed technology generally relates to a memory device, and more particularly to a ferroelectric memory device and a method of operating the memory device. According to one aspect, a memory device comprises a bit cell. The bit cell comprises a write transistor, a read transistor and a ferroelectric capacitor. A write word line is connected to a gate terminal of the write transistor. A write bit line is connected to a first terminal of the write transistor. A read bit line connected to a terminal of the read transistor. A first control line is connected to a first electrode of the ferroelectric capacitor. A second terminal of the write transistor is connected to the gate terminal of the read transistor, and a second electrode of the ferroelectric capacitor is connected to the second terminal.

公开(公告)号：US10090036B2

公开(公告)日：2018-10-02

申请号：US15385593

申请日：2016-12-20

Applicant: IMEC VZW

Inventor： Jan Van Houdt

IPC: G11C11/22 ,  H01L27/1159 ,  G11C16/04

Abstract: The disclosed technology relates generally to non-volatile memory devices, and more particularly to ferroelectric non-volatile memory devices. In one aspect, a non-volatile memory cell includes a pinch-off ferroelectric memory FET and at least one select device electrically connected in series to the pinch-off ferroelectric memory FET.

公开(公告)号：US20170178698A1

公开(公告)日：2017-06-22

申请号：US15369204

申请日：2016-12-05

Applicant: IMEC VZW

Inventor： Jan Van Houdt

IPC: G11C7/06

CPC classification number: G11C7/06 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/28 ,  H01L28/00 ,  H01L29/516 ,  H01L29/78 ,  H01L29/78391 ,  H01L29/788 ,  H01L29/792

Abstract: The present disclosure relates to a memory cell, a memory array, and methods for writing a memory cell. In an example embodiment, a memory cell comprises a first transistor, a second transistor, and a differential sense amplifier. The first transistor is a Vt-modifiable n-channel transistor and the second transistor is a Vt-modifiable p-channel transistor, each transistor having first and second main electrodes. The first main electrodes of the first and second transistors are connected together. The differential sense amplifier is connected to the second main electrodes of the first and the second transistor. The differential sense amplifier is adapted for sensing the current difference between the first transistor and the second transistor.