公开(公告)号：US20200168500A1

公开(公告)日：2020-05-28

申请号：US16695776

申请日：2019-11-26

Applicant: IMEC VZW

Inventor： Frederic Lazzarino ,  Guillaume Bouche ,  Juergen Boemmels

IPC: H01L21/768 ,  H01L21/02

Abstract: A method for forming an interconnection structure for a semiconductor device is provided. The method includes: (i) forming a conductive layer on an insulating layer; (ii) forming above the conductive layer a first set of mandrel lines of a first material; (iii) forming a set of spacer lines of a second material different from the first material, wherein the spacer lines of the second material are formed on sidewalls of the first set of mandrel lines; (iv) forming a second set of mandrel lines of a third material different from the first and second materials, wherein the second set of mandrel lines fill gaps between spacer lines of the set of spacer lines; (v) cutting at least a first mandrel line of the second set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the second set of mandrel lines selectively to the set of spacer lines and the first set of mandrel lines, cutting at least a first mandrel line of the first set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the first set of mandrel lines selectively to the set of spacer lines and the second set of mandrel lines; (vi) removing the set of spacer lines, selectively to the first and second sets of mandrel lines, thereby forming an alternating pattern of mandrel lines of the first set of mandrel lines and mandrel lines of the second set of mandrel lines; and (vii) patterning the conductive layer to form a set of conductive lines, wherein the patterning comprises etching while using the alternating pattern of mandrel lines of the first and second sets of mandrel lines as an etch mask.

公开(公告)号：US20200135568A1

公开(公告)日：2020-04-30

申请号：US16663796

申请日：2019-10-25

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Julien Ryckaert

IPC: H01L21/8234 ,  H01L29/423

Abstract: The present disclosure relates to three dimensional (3D) transistor structures and methods of forming the same. In an aspect, a method comprises providing a vertical stack of alternating layers of channel material and dummy material, forming a first set of fins on the stack, and forming a second fin above the first set of fins, the second fin extending orthogonal to the first set of fins. Further, the first set of fins is cut into a set of fin portions, using the second fin and a first sidewall spacers as an etch mask, and second sidewall spacers are formed on the second fin. These structures are used to form a 3D structure of channel regions and source/drain regions forming transistor structures. Advantageously, the 3D semiconductor structure is manufactured using a relatively low number of mask layers per transistor which decreases manufacturing costs.

公开(公告)号：US20190035795A1

公开(公告)日：2019-01-31

申请号：US16049528

申请日：2018-07-30

Applicant: IMEC vzw

Inventor： Juergen Boemmels

IPC: H01L27/11 ,  H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/36 ,  H01L29/06

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions. A connection region is formed in the bottom electrode region underneath the first, second and third regions, wherein the connection region and the first and third regions are doped with a dopant of a same type. A resistance of a path extending between the first and the third regions through the connection region is lower than a resistance of a path extending between the first and the third regions through the second region. A second aspect is a method of forming the semiconductor device of the first aspect.

公开(公告)号：US20230197726A1

公开(公告)日：2023-06-22

申请号：US18064508

申请日：2022-12-12

Applicant: IMEC VZW

Inventor： Book Teik Chan ,  Dunja Radisic ,  Anne Vandooren ,  Juergen Boemmels

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823857 ,  H01L21/823828 ,  H01L29/0673

Abstract: Example embodiments relate to methods for forming a stacked FET device. An example method includes forming a bottom FET device that includes a source, a drain, at least one channel layer between the source and drain, and a bottom gate electrode arranged along the at least one channel layer. The method also includes forming a bonding layer over the bottom FET. Additionally, the method includes forming a top FET device on the bonding layer. Forming the top FET device includes forming a device layer structure. The device layer structure includes at least one channel layer of a channel semiconductor material and a top sacrificial layer of a sacrificial semiconductor material. Further, the method includes replacing the top sacrificial layer with a dummy layer of a dielectric dummy material, forming a gate-to-gate contact trench, depositing gate electrode material, and forming a source and a drain of the top FET device.

公开(公告)号：US11515399B2

公开(公告)日：2022-11-29

申请号：US17112844

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L21/02 ,  H01L21/8238

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

公开(公告)号：US20210193821A1

公开(公告)日：2021-06-24

申请号：US17112844

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L21/02 ,  H01L21/8238

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

公开(公告)号：US10566236B2

公开(公告)日：2020-02-18

申请号：US15979183

申请日：2018-05-14

Applicant: IMEC VZW

Inventor： Juergen Boemmels

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/06 ,  H01L21/311 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8234

Abstract: The disclosed technology generally relates semiconductor devices and more particularly to vertical channel devices and methods of forming the vertical channel devices. According to one aspect, a method of forming a vertical channel device includes forming on a semiconductor substrate a plurality of vertical channel structures. The method additionally includes forming gates, where each of the gates wraps around one of the vertical channel structures. The method additionally includes embedding the gates in a first dielectric layer and exposing top portions of the vertical channel structures. The method additionally includes forming top electrodes on corresponding top portions of the vertical channel structures. The method additionally includes forming sidewall etch barriers on sidewalls of each of the top electrodes. The method additionally includes forming a second dielectric layer covering the first dielectric layer and the top electrodes. The method additionally includes etching a set of vertically extending gate contact holes through the first and second dielectric layers and selectively against the sidewall etch barriers, where each of the gate contact holes exposes one of the gates adjacent to one of the top electrodes. The method further includes filling the set of gate contact holes with a conductive material. A vertical channel device fabricated using the method is also disclosed according another aspect.

公开(公告)号：US20200027780A1

公开(公告)日：2020-01-23

申请号：US16518361

申请日：2019-07-22

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Christopher Wilson ,  Juergen Boemmels

IPC: H01L21/768 ,  H01L23/522

Abstract: A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level.

公开(公告)号：US20190386011A1

公开(公告)日：2019-12-19

申请号：US16441725

申请日：2019-06-14

Applicant: IMEC vzw

Inventor： Pieter Weckx ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L27/11 ,  G11C5/02 ,  G11C5/06 ,  G11C11/412 ,  H01L21/822 ,  H01L21/8238

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.

公开(公告)号：US20180342616A1

公开(公告)日：2018-11-29

申请号：US15980611

申请日：2018-05-15

Applicant: IMEC vzw

Inventor： Juergen Boemmels

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/15 ,  H01L27/11

CPC classification number: H01L29/7827 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/1104 ,  H01L29/152 ,  H01L29/66666

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to vertical channel devices and a method of making the same. In one aspect, a method of forming vertical channel devices includes forming a first vertical channel structure extending from a first bottom electrode region and a second vertical channel structure extending from a second bottom electrode region. The first and the second vertical channel structures protrude from a dielectric layer covering the first and second bottom electrode regions. The method additionally comprises forming a first hole exposing the first bottom electrode region and a second hole exposing the second bottom electrode region, where the first and the second holes extending vertically through the dielectric layer. The method additionally includes forming a conductive pattern including a set of discrete pattern parts on the dielectric layer. Forming the conductive pattern includes forming a first pattern part including a first gate portion wrapping around a protruding portion of the first vertical channel structure, where a first bottom electrode contact portion is arranged in the second hole, and a first cross-coupling portion extending between the first bottom electrode contact portion and the first gate portion. Forming the conductive pattern additionally includes forming a second pattern part including a second gate portion wrapping around a protruding portion of the second vertical channel structure, where a second bottom electrode contact portion is arranged in the first hole, and a cross-coupling portion extending between the second bottom electrode contact portion and the second gate portion.