公开(公告)号：US20140103354A1

公开(公告)日：2014-04-17

申请号：US14049209

申请日：2013-10-09

Applicant: Industrial Technology Research Institute

Inventor： Chih-Wei Hu ,  Chen-Zi Liao ,  Yen-Hsiang Fang ,  Rong Xuan

IPC: H01L29/205

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/2003 ,  H01L33/12 ,  H01L33/32

Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate includes a cubic silicon carbon nitride (SiCN) layer. The buffer layer is disposed on the nucleation layer. The nitride semiconductor layer is disposed on the buffer layer.

Abstract translation: 提供了包括硅衬底，成核层，缓冲层和氮化物半导体层的氮化物半导体结构。 设置在硅衬底上的成核层包括立方氮化硅（SiCN）层。 缓冲层设置在成核层上。 氮化物半导体层设置在缓冲层上。

公开(公告)号：US20150137332A1

公开(公告)日：2015-05-21

申请号：US14583780

申请日：2014-12-29

Applicant: Industrial Technology Research Institute

Inventor： Yi-Keng Fu ,  Rong Xuan ,  Hsun-Chih Liu

IPC: H01L33/64 ,  H01L33/22

CPC classification number: H01L33/642 ,  H01L33/002 ,  H01L33/007 ,  H01L33/025 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/20 ,  H01L33/22 ,  Y10T428/24562

Abstract: A carrier for carrying a semiconductor layer having a growth surface and at least one nano-patterned structure on the growth surface is provided. The at least one nano-patterned structure on the growth surface of the carrier has a plurality of mesas, a recess is formed between two adjacent mesas, in which a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm.

Abstract translation: 提供了用于在生长表面上承载具有生长表面和至少一个纳米图案结构的半导体层的载体。 在载体的生长表面上的至少一个纳米图案结构具有多个台面，在两个相邻的台面之间形成凹部，其中凹部的深度范围为10nm至500nm， 台面范围为10nm至800nm。

公开(公告)号：US20130168687A1

公开(公告)日：2013-07-04

申请号：US13686935

申请日：2012-11-28

Applicant: Industrial Technology Research Institute

Inventor： Wei-Hung Kuo ,  Suh-Fang Lin ,  Rong Xuan

IPC: H01L29/20 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/28264 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/452 ,  H01L29/778 ,  H01L29/7786

Abstract: Provided is an enhancement mode GaN-based transistor device including an epitaxial stacked layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer. Besides, the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer. With such structure, the enhancement mode GaN-based transistor device can effectively suppress generation of the gate leakage current.

Abstract translation: 提供了一种增强型GaN基晶体管器件，其包括设置在衬底上的外延层叠层; 设置在所述外延层叠层的表面上的源极层和漏极层; 设置在源极层和漏极层之间的p型金属氧化物层; 以及设置在p型金属氧化物层上的栅极层。 此外，p型金属氧化物层包括设置在外延层叠层的表面上的主体部分和连接主体部分并延伸到外延层叠层中的多个延伸部分。 利用这种结构，增强型GaN基晶体管器件可以有效地抑制栅极漏电流的产生。