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    Compact high speed duty cycle corrector
    12.
    发明授权
    Compact high speed duty cycle corrector 有权

    公开(公告)号：US09882570B1

    公开(公告)日：2018-01-30

    申请号：US15389830

    申请日：2016-12-23

    Applicant: INPHI CORPORATION

    Inventor： Simon Forey ,  Rajasekhar Nagulapalli ,  Parmanand Mishra

    IPC: H03L7/08 ,  H03K5/156 ,  H03G3/20 ,  H04L27/01

    CPC classification number: H03L7/0807 ,  H03G3/20 ,  H03K5/1565 ,  H04L27/01

    Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

    Variable gain amplifiers for communication systems
    14.
    发明授权
    Variable gain amplifiers for communication systems 有权

    公开(公告)号：US10763810B2

    公开(公告)日：2020-09-01

    申请号：US16810651

    申请日：2020-03-05

    Applicant: INPHI CORPORATION

    Inventor： Simon Forey ,  Rajasekhar Nagulapalli ,  Parmanand Mishra

    IPC: H03G3/22 ,  H03F3/45 ,  H03G3/30 ,  H03G1/00 ,  H03G3/00 ,  H03G7/06

    Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

    Compact high speed duty cycle corrector
    15.
    发明授权
    Compact high speed duty cycle corrector 有权

    公开(公告)号：US10333527B2

    公开(公告)日：2019-06-25

    申请号：US16154522

    申请日：2018-10-08

    Applicant: INPHI CORPORATION

    Inventor： Simon Forey ,  Rajasekhar Nagulapalli ,  Parmanand Mishra

    IPC: H04L27/01 ,  H03L7/08 ,  H03K5/156 ,  H03G3/20

    Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

    Differential circuits with constant GM bias
    17.
    发明授权
    Differential circuits with constant GM bias 有权

    公开(公告)号：US10103698B2

    公开(公告)日：2018-10-16

    申请号：US15633521

    申请日：2017-06-26

    Applicant: INPHI CORPORATION

    Inventor： Rajasekhar Nagulapalli ,  Simon Forey ,  Parmanand Mishra

    IPC: H03F3/45 ,  H03F1/34

    Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, embodiments of the present invention provide a differential amplifier that has a differential amplifier section, a current source, and a feedback section. The differential amplifier section comprises NMOS transistors that receives two voltage inputs and generate a differential output. The current source provides a long tail for the differential amplifier section. The feedback section generates a feedback voltage based on a reference bias voltage. The feedback voltage is used by an amplifier to control the current source and to keep the biasing and gain of the differential amplifier substantially constant. There are other embodiments as well.

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