公开(公告)号：US11189614B2

公开(公告)日：2021-11-30

申请号：US15923885

申请日：2018-03-16

Applicant: INTEL CORPORATION

Inventor： Leonard Guler ,  Elliot Tan

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308

Abstract: A grating structure has a plurality of grating members that extend upward from a base in a spaced-apart parallel relationship and include an end member. For example, the grating structure is a plurality of semiconductor fins on a base. The base can be any structure underlying the grating members. The grating members have a member width and a member height. Adjacent grating members are spaced by a grating spacing. A process artifact is adjacent the end member and is spaced from the end member by a horizontal distance consistent with the member spacing. In some cases, the process artifact can be a stub of a second material on or otherwise extending from the base adjacent an end member of the grating structure. In other cases, the process artifact can be a recess in or otherwise extending into the base adjacent an end member of the grating structure.

公开(公告)号：US20210335791A1

公开(公告)日：2021-10-28

申请号：US17368329

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/786 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US12148734B2

公开(公告)日：2024-11-19

申请号：US17117350

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le ,  Thoe Michaelos

IPC: H01L25/065 ,  H10B12/00 ,  H10B10/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H10B63/00

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

公开(公告)号：US12114479B2

公开(公告)日：2024-10-08

申请号：US17368329

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC: H10B12/00 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/786

CPC classification number: H10B12/31 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L29/78696 ,  H10B12/30

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20240071955A1

公开(公告)日：2024-02-29

申请号：US17899670

申请日：2022-08-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Shem Ogadhoh ,  Swaminathan Sivakumar ,  Sagar Suthram ,  Elliot Tan

IPC: H01L23/00 ,  H01L23/528 ,  H01L27/085

CPC classification number: H01L23/564 ,  H01L23/528 ,  H01L27/085

Abstract: Described herein is full wafer device that includes a computing logic formed over a substrate and two directional indicators formed in the substrate. The computing logic is arranged as a plurality of dies having a first die edge direction and a second die edge direction perpendicular to the first die edge direction. The computing logic further includes an angled feature extending in a feature direction, the feature direction different from the first die edge direction and the second die edge direction. The first directional indicator formed in the substrate indicates the first die edge direction. The second directional indicator formed in the substrate indicates the feature direction.

公开(公告)号：US11888043B2

公开(公告)日：2024-01-30

申请号：US18093443

申请日：2023-01-05

Applicant: Intel Corporation

Inventor： Elliot Tan

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/7856

Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.

公开(公告)号：US20220189957A1

公开(公告)日：2022-06-16

申请号：US17117978

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le

IPC: H01L27/108 ,  G11C11/402 ,  H01L29/24

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

公开(公告)号：US11056492B1

公开(公告)日：2021-07-06

申请号：US16724691

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Elliot Tan ,  Szuya S. Liao ,  Tahir Ghani ,  Swaminathan Sivakumar ,  Rajesh Kumar

IPC: G11C11/34 ,  H01L27/108 ,  G11C5/04 ,  G11C5/10 ,  G11C11/402

Abstract: Described herein are memory arrays where some memory cells include access transistors with one front-side and one back-side source/drain (S/D) contacts. An example memory array further includes a bitline, coupled to the first S/D region of the access transistor of a first memory cell of the memory array, and a plateline, coupled to a first capacitor electrode of a storage capacitor of the first memory cell. Because the access transistor is a transistor with one front-side and one back-side S/D contacts, the bitline may be provided in a first layer, the channel material—in a second layer, and the plateline—in a third layer, where the second layer is between the first layer and the third layer, which may allow increasing the density of memory cells in a memory array, or, conversely, reducing the footprint area of a memory array with a given density of memory cells.

公开(公告)号：US20210193666A1

公开(公告)日：2021-06-24

申请号：US16724691

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Elliot Tan ,  Szuya S. Liao ,  Tahir Ghani ,  Swaminathan Sivakumar ,  Rajesh Kumar

IPC: H01L27/108 ,  G11C11/402 ,  G11C5/10 ,  G11C5/04

Abstract: Described herein are memory arrays where some memory cells include access transistors with one front-side and one back-side source/drain (S/D) contacts. An example memory array further includes a bitline, coupled to the first S/D region of the access transistor of a first memory cell of the memory array, and a plateline, coupled to a first capacitor electrode of a storage capacitor of the first memory cell. Because the access transistor is a transistor with one front-side and one back-side S/D contacts, the bitline may be provided in a first layer, the channel material—in a second layer, and the plateline—in a third layer, where the second layer is between the first layer and the third layer, which may allow increasing the density of memory cells in a memory array, or, conversely, reducing the footprint area of a memory array with a given density of memory cells.