公开(公告)号：US11430814B2

公开(公告)日：2022-08-30

申请号：US16957047

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L27/22 ,  H01L27/24 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US20220093546A1

公开(公告)日：2022-03-24

申请号：US17025181

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Kevin P. O'Brien ,  Kimin Jun ,  Han Wui Then ,  Mohammad Enamul Kabir ,  Gerald S. Pasdast ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L49/02 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US11251158B2

公开(公告)日：2022-02-15

申请号：US16633543

申请日：2017-09-25

Applicant: INTEL CORPORATION

Inventor： Anup Pancholi ,  Kimin Jun

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.

公开(公告)号：US11121691B2

公开(公告)日：2021-09-14

申请号：US16348830

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Kimin Jun ,  Edris Mohammed

IPC: H03H3/02 ,  H03H9/17

Abstract: The RF filters used in conventional mobile devices often include resonator structures, which often require free-standing air-gap structure to prevent mechanical vibrations of the resonator from being damped by a bulk material. A method for fabricating a resonator structure comprises depositing a non-conformal thin-film to the resonator structure to seal air gap cavities in the resonator structure.

公开(公告)号：US10797139B2

公开(公告)日：2020-10-06

申请号：US16457728

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC: H01L21/00 ,  H01L23/522 ,  H01L27/00 ,  H01L29/00 ,  H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

公开(公告)号：US20200266218A1

公开(公告)日：2020-08-20

申请号：US16279693

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow ,  Kimin Jun

IPC: H01L27/12 ,  H01L21/84

Abstract: Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.

公开(公告)号：US10700039B2

公开(公告)日：2020-06-30

申请号：US15122382

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Donald W. Nelson ,  M. Clair Webb ,  Patrick Morrow ,  Kimin Jun

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L25/00 ,  H01L23/427

Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

公开(公告)号：US10439057B2

公开(公告)日：2019-10-08

申请号：US15329216

申请日：2014-09-09

Applicant: INTEL CORPORATION

Inventor： Kimin Jun ,  Sansaptak Dasgupta ,  Alejandro X. Levander ,  Patrick Morrow

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/66 ,  H01L21/762

Abstract: A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.

公开(公告)号：US10186484B2

公开(公告)日：2019-01-22

申请号：US15122913

申请日：2014-09-27

Applicant: Intel Corporation

Inventor： Donald W. Nelson ,  Patrick Morrow ,  Kimin Jun

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L29/78

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.

公开(公告)号：US10014374B2

公开(公告)日：2018-07-03

申请号：US15026271

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Patrick Morrow

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L21/762

CPC classification number: H01L29/1054 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/8258 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L29/78

Abstract: In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.