公开(公告)号：US10908673B2

公开(公告)日：2021-02-02

申请号：US15891081

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pascal Meinerzhagen ,  Stephen Kim ,  Dongmin Yoon ,  Minki Cho ,  Muhammad Khellah

IPC: G06F1/32 ,  G05F1/563 ,  G05F1/59 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/324

Abstract: An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.

公开(公告)号：US10707877B1

公开(公告)日：2020-07-07

申请号：US16455162

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Turbo Majumder ,  Minki Cho ,  Carlos Tokunaga ,  Praveen Mosalikanti ,  Nasser A. Kurd ,  Muhammad M. Khellah

IPC: G06F1/08 ,  H03L5/00 ,  H03L7/099

Abstract: Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.

公开(公告)号：US10454476B2

公开(公告)日：2019-10-22

申请号：US16145598

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

IPC: H03K19/00

Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

公开(公告)号：US20190243440A1

公开(公告)日：2019-08-08

申请号：US15891081

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pascal Meinerzhagen ,  Stephen Kim ,  Dongmin Yoon ,  Minki Cho ,  Muhammad Khellah

IPC: G06F1/32 ,  G05F1/563 ,  G05F1/59

CPC classification number: G06F1/3296 ,  G05F1/563 ,  G05F1/59 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287

Abstract: An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.

公开(公告)号：US10243563B2

公开(公告)日：2019-03-26

申请号：US15394296

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Andrea Bonetti ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Minki Cho ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H03L5/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/21

Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

公开(公告)号：US20190044512A1

公开(公告)日：2019-02-07

申请号：US16145598

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

IPC: H03K19/00

CPC classification number: H03K19/0016 ,  H03K19/0013

Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

公开(公告)号：US20180287592A1

公开(公告)日：2018-10-04

申请号：US15477913

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Minki Cho ,  Jaydeep Kulkarni ,  Carlos Tokunaga ,  Muhammad Khellah ,  James Tschanz

IPC: H03K3/011 ,  H03K3/012 ,  G11C11/419 ,  G06F1/32

CPC classification number: H03K3/011 ,  G06F1/3275 ,  G11C11/413 ,  G11C11/419 ,  G11C29/04 ,  H03K3/012

Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.