公开(公告)号：US09838967B2

公开(公告)日：2017-12-05

申请号：US14595085

申请日：2015-01-12

Applicant: Intel Corporation

Inventor： Jaya L. Jeyaseelan ,  Jim Walsh ,  Robert E. Gough ,  Barnes Cooper ,  Neil W. Songer

IPC: H04W52/02 ,  G06F1/32 ,  H04L12/26

CPC classification number: H04W52/0225 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3296 ,  G06F13/4282 ,  H04L43/0858 ,  Y02D10/151 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/23

Abstract: An apparatus is provided that includes a transceiver to transmit and receive data between an upstream device and the apparatus, and further includes service latency reporting logic coupled to the transceiver to provide a service latency tolerance value of the apparatus to the upstream device, the service latency tolerance value corresponding to an activity state of the apparatus. The service latency tolerance value for an idle activity state can be greater than the service latency tolerance value for an active activity state.

公开(公告)号：US20170329377A1

公开(公告)日：2017-11-16

申请号：US15668771

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Vasudevan Srinivasan ,  Eugene Gorbatov ,  Andrew D. Henroid ,  Barnes Cooper ,  David W. Browning ,  Guy M. Therien ,  Neil W. Songer ,  Krishnakanth V. Sistla ,  James G. Hermerding, II

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/20 ,  G06F15/00

Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

公开(公告)号：US10678199B2

公开(公告)日：2020-06-09

申请号：US15191123

申请日：2016-06-23

Applicant: INTEL CORPORATION

Inventor： Barnes Cooper ,  Neil W. Songer

IPC: G06F1/32 ,  G05B15/02 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/46 ,  G06F1/20 ,  G06F11/30 ,  G06F1/3234

Abstract: Standby power entry can be performed without latency tolerance information. The embodiments disclosed herein enable a power delivery system of a computing system to enter the requested low power state while ignoring any latency tolerance information throughout the platform. For example, an operating system (OS) can request a Forced Cx state (also known as a Forced C state), such as a Forced C10 state, allowing the system to ignore any latency tolerance information throughout the platform. This Forced Cx state can be used as a test mechanism to determine if a problematic device or integrated circuit is blocking entry into the low power state.

公开(公告)号：US10182398B2

公开(公告)日：2019-01-15

申请号：US15453208

申请日：2017-03-08

Applicant: Intel Corporation

Inventor： Jaya L. Jeyaseelan ,  Jim Walsh ,  Robert E. Gough ,  Barnes Cooper ,  Neil W. Songer

IPC: H04W52/02 ,  G06F13/42 ,  G06F1/32 ,  H04L12/26 ,  G06F1/20

Abstract: An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.