公开(公告)号：US10509738B2

公开(公告)日：2019-12-17

申请号：US15201373

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Narayan Ranganathan ,  Pete D. Vogt

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H04L12/803 ,  H04L29/08 ,  G06F15/173 ,  H04L12/933

Abstract: An extension of node architecture and proxy requests enables a node to expose memory computation capability to remote nodes. A remote node can request execution of an operation by a remote memory computation resource, and the remote memory computation resource can execute the request locally and return the results of the computation. The node includes processing resources, a fabric interface, and a memory subsystem including a memory computation resource. The local execution of the request by the memory computation resource can reduce latency and bandwidth concerns typical with remote requests.

公开(公告)号：US10242717B2

公开(公告)日：2019-03-26

申请号：US15808390

申请日：2017-11-09

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Pete D. Vogt

IPC: G11C8/00 ,  G11C5/06 ,  G06F1/18 ,  H01R12/71 ,  H05K1/18 ,  G11C5/04 ,  H05K1/14 ,  H05K1/02

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

公开(公告)号：US20170199830A1

公开(公告)日：2017-07-13

申请号：US15196014

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  George Vergis ,  Christopher E. Cox ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F13/16 ,  G11C11/4096 ,  G06F13/40 ,  G11C14/00

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4096

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.