公开(公告)号：US10249597B2

公开(公告)日：2019-04-02

申请号：US15283055

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Kalyan C. Kolluru ,  Pete D. Vogt ,  Christopher J. Nelson ,  Amande B. Trang ,  Uddalak Bhattacharya

IPC: G11C5/06 ,  H01L25/065 ,  H01L25/18 ,  G11C5/02 ,  G11C29/02 ,  G11C29/12 ,  G11C29/48 ,  G11C29/00

Abstract: Systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems are described. A stacked semiconductor package includes a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSV s) formed through the one or more memory dies; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; and a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.

公开(公告)号：US10146711B2

公开(公告)日：2018-12-04

申请号：US15196014

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  George Vergis ,  Christopher E. Cox ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F13/16 ,  G11C14/00 ,  G11C11/4096 ,  G06F13/40

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US09335373B2

公开(公告)日：2016-05-10

申请号：US14306025

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Pete D. Vogt

IPC: G01R31/317 ,  G11C11/40 ,  G11C7/10 ,  G11C11/4093 ,  G06F11/07

CPC classification number: G01R31/31726 ,  G06F11/0793 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1066 ,  G11C11/4093

Abstract: A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit.

Abstract translation: 存储器模块可以具有具有多个重新驱动路径的重新启动电路，存储器件和偏移电路。 偏移电路可以与多个重新驱动路径分开。 歪斜电路可以耦合在多个重新驱动路径和存储器件之间，以选择性地使在重新驱动电路中接收的数据失真。

公开(公告)号：US10216657B2

公开(公告)日：2019-02-26

申请号：US15283186

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Pete D. Vogt

IPC: G06F1/00 ,  G06F13/16 ,  G06F1/18 ,  G11C5/06

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on thePCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

公开(公告)号：US20180210674A1

公开(公告)日：2018-07-26

申请号：US15836840

申请日：2017-12-09

Applicant: Intel Corporation

Inventor： Pete D. Vogt

IPC: G06F3/06 ,  G11C5/06 ,  G11C5/02

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0683 ,  G06F2003/0697 ,  G11C5/025 ,  G11C5/063

Abstract: Methods and apparatus to provide heterogeneous memory die stacking for energy efficient computing are described. In one embodiment, a Phase Change Memory with Switch (PCMS) die is coupled to a Dynamic Random Access Memory (DRAM) die and a Central Processing Unit (CPU) die. CPU checkpointing state data is stored in the PCMS die first before transferring the checkpointing data to a backup media at a later and more extended time. Other embodiments are also disclosed and claimed.

公开(公告)号：US09818457B1

公开(公告)日：2017-11-14

申请号：US15283167

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Pete D. Vogt

IPC: G11C8/00 ,  G11C5/06 ,  H01R12/71 ,  G06F1/18 ,  H05K1/18

CPC classification number: G11C5/06 ,  G06F1/18 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  H01R12/716 ,  H05K1/0295 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/09409 ,  H05K2201/10159

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

公开(公告)号：US10599592B2

公开(公告)日：2020-03-24

申请号：US16283597

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Pete D. Vogt

IPC: G06F1/18 ,  G11C5/06 ,  G06F13/16

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

公开(公告)号：US10120749B2

公开(公告)日：2018-11-06

申请号：US15282793

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Pete D. Vogt

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/4093

Abstract: ECC (error checking and correction) can be extended to allow an ECC code to correct memory subarray errors. A memory device includes multiple input/output (I/O) connectors to interface with an external device such as a controller. The memory device includes multiple arrays or subarrays that are specifically mapped to I/O connectors instead of arbitrarily routed. As such, the data paths of the memory subarrays can be exclusively routed to a specific I/O connector. The I/O connector can be uniquely associated with a single memory subarray, or multiple memory subarrays can be mapped to a specific I/O connector. The mapping is in accordance with an error checking and correcting (ECC) code matrix, where a code of the ECC code matrix corresponding to the specific I/O connector is to check and correct data corruption errors and I/O errors for the associated one or multiple memory subarrays.

公开(公告)号：US10031802B2

公开(公告)日：2018-07-24

申请号：US13930600

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Pete D. Vogt

IPC: G06F11/10

Abstract: Apparatus, systems, and methods to embed ECC data with cacheline data in a memory page are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive a request to read or write data to a memory device, wherein the data is mapped to a memory page comprising a plurality of cache lines, displace at least a portion of the plurality of cache lines to embed error correction code information with the data, and remap the portion of the plurality of cache lines to another memory location, and retrieve or store the data and the error correction code information on the memory page. Other embodiments are also disclosed and claimed.

公开(公告)号：US10592445B2

公开(公告)日：2020-03-17

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox ,  Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F11/16 ,  G06F13/16 ,  G11C11/4096 ,  G06F13/40 ,  G11C14/00 ,  G11C5/04 ,  G11C7/10

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.