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    DUAL BUS STANDARD SWITCHING BUS CONTROLLER
    11.
    发明申请
    DUAL BUS STANDARD SWITCHING BUS CONTROLLER 审中-公开
    双总线标准开关总线控制器

    公开(公告)号：US20160085707A1

    公开(公告)日：2016-03-24

    申请号：US14801880

    申请日：2015-07-17

    Applicant: Intel Corporation

    Inventor： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

    IPC: G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/4022 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4282

    Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

    Abstract translation: 在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。 公开和要求保护其他实施例。

    System, apparatus and method for synchronizing multiple virtual link states over a package interconnect
    13.
    发明授权
    System, apparatus and method for synchronizing multiple virtual link states over a package interconnect 有权

    公开(公告)号：US11442876B2

    公开(公告)日：2022-09-13

    申请号：US16426361

    申请日：2019-05-30

    Applicant: Intel Corporation

    Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

    Virtualized link states of multiple protocol layer package interconnects
    14.
    发明授权
    Virtualized link states of multiple protocol layer package interconnects 有权

    公开(公告)号：US10776302B2

    公开(公告)日：2020-09-15

    申请号：US16373472

    申请日：2019-04-02

    Applicant: Intel Corporation

    Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

    IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

    Dual bus standard switching bus controller
    15.
    发明授权
    Dual bus standard switching bus controller 有权

    公开(公告)号：US10229080B2

    公开(公告)日：2019-03-12

    申请号：US14801880

    申请日：2015-07-17

    Applicant: Intel Corporation

    Inventor： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

    IPC: G06F13/20 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

    Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

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