公开(公告)号：US20180375433A1

公开(公告)日：2018-12-27

申请号：US15632086

申请日：2017-06-23

Applicant: INTEL CORPORATION

Inventor： Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M3/1582 ,  G05F1/67 ,  H02M1/08 ,  H02M2001/0003 ,  H02M2001/0009 ,  H02M2001/0025

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

公开(公告)号：US12047485B2

公开(公告)日：2024-07-23

申请号：US17132365

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Xiaosen Liu ,  Harish Krishnamurthy ,  Sanu Mathew ,  Vikram Suresh

IPC: H04L9/00 ,  G05F1/46 ,  G05F1/575 ,  G05F1/59 ,  G06F1/26 ,  H04L9/06 ,  H04L9/08

CPC classification number: H04L9/003 ,  G06F1/26 ,  H04L9/0631 ,  H04L2209/08

Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.

公开(公告)号：US11940824B2

公开(公告)日：2024-03-26

申请号：US17100603

申请日：2020-11-20

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/46 ,  G05F1/67

CPC classification number: G05F1/56 ,  G05F1/462 ,  G05F1/67

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

公开(公告)号：US11444532B2

公开(公告)日：2022-09-13

申请号：US16727759

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Vivek De

IPC: G05F1/56 ,  G05F1/563 ,  G05F1/575 ,  G05F1/59 ,  H02M3/158 ,  H02M1/088 ,  H02N13/00 ,  H03L5/00

Abstract: A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.

公开(公告)号：US20220200784A1

公开(公告)日：2022-06-23

申请号：US17132365

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Xiaosen Liu ,  Harish Krishnamurthy ,  Sanu Mathew ,  Vikram Suresh

IPC: H04L9/00 ,  G06F1/26 ,  H04L9/06

Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.

公开(公告)号：US10897364B2

公开(公告)日：2021-01-19

申请号：US15846045

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Vivek De ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Khondker Ahmed ,  Sriram Vangal ,  Vaibhav Vaidya ,  Turbo Majumder ,  Christopher Schaef ,  Suhwan Kim ,  Xiaosen Liu ,  Nachiket Desai

IPC: H04L9/32

Abstract: Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

公开(公告)号：US20190317536A1

公开(公告)日：2019-10-17

申请号：US16450873

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Harish Krishnamurthy ,  Krishnan Ravichandran ,  Vivek De ,  Scott Chiu ,  Claudia Patricia Barrera Gonzalez ,  Jing Han ,  Rajasekhara Madhusudan Narayana Bhatla

IPC: G05F1/56 ,  G05F1/67 ,  G05F1/46

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.