公开(公告)号：US11176994B2

公开(公告)日：2021-11-16

申请号：US17001432

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418 ,  G11C7/22

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

公开(公告)号：US10739804B2

公开(公告)日：2020-08-11

申请号：US15712813

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Sriram R. Vangal ,  Turbo Majumder ,  Vivek De

IPC: G05F1/66 ,  G05F1/46 ,  G06F1/3296 ,  H02M3/158 ,  H02M1/08 ,  H02M3/157

Abstract: Various embodiments of the invention may be used to find a combination of voltage and frequency that results in a minimum amount of energy consumption in a digital system, including energy consumed by the system's voltage regulator (VR). The process may involve finding a separate point of minimum energy consumption for each of several different modes of the VR, where a mode is the ratio of Vin to Vout for that VR. The smallest value of those points may then be selected as the overall minimum. The process for making this determination may be performed in situ while the device is in operation, and may encompass changes in operational temperature, load, and process variations.

公开(公告)号：US10530254B2

公开(公告)日：2020-01-07

申请号：US15632086

申请日：2017-06-23

Applicant: INTEL CORPORATION

Inventor： Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

公开(公告)号：US10897364B2

公开(公告)日：2021-01-19

申请号：US15846045

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Vivek De ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Khondker Ahmed ,  Sriram Vangal ,  Vaibhav Vaidya ,  Turbo Majumder ,  Christopher Schaef ,  Suhwan Kim ,  Xiaosen Liu ,  Nachiket Desai

IPC: H04L9/32

Abstract: Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

公开(公告)号：US10892012B2

公开(公告)日：2021-01-12

申请号：US16110990

申请日：2018-08-23

Applicant: INTEL CORPORATION

Inventor： Turbo Majumder ,  Somnath Paul ,  Charles Augustine ,  Muhammad M. Khellah

IPC: G11C15/00 ,  G06T1/60 ,  G11C15/04

Abstract: An apparatus, vision processing unit, and method are provided for clustering motion events in a content addressable memory. A motion event is received including coordinates in an image frame that have experienced a change and a timestamp of the change. A determination is made as to whether determine whether there is a valid entry in the memory having coordinates within a predefined range of coordinates included in the motion event. In response to a determination that there is the valid entry having the coordinates within the predefined range of coordinates included in the motion event, write to the valid entry the coordinates and the timestamp in the motion event.

公开(公告)号：US10707877B1

公开(公告)日：2020-07-07

申请号：US16455162

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Turbo Majumder ,  Minki Cho ,  Carlos Tokunaga ,  Praveen Mosalikanti ,  Nasser A. Kurd ,  Muhammad M. Khellah

IPC: G06F1/08 ,  H03L5/00 ,  H03L7/099

Abstract: Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.

公开(公告)号：US11908542B2

公开(公告)日：2024-02-20

申请号：US16725747

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Turbo Majumder ,  Iqbal Rajwani ,  Andrew Lines ,  Altug Koker ,  Lakshminarayanan Striramassarma ,  Muhammad Khellah

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1048 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22

Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.

公开(公告)号：US11411491B2

公开(公告)日：2022-08-09

申请号：US16642853

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Vivek De ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Khondker Ahmed ,  Sriram Vangal ,  Vaibhav Vaidya ,  Turbo Majumder ,  Christopher Schaef ,  Suhwan Kim ,  Xiaosen Liu ,  Nachiket Desai

IPC: H02M3/158 ,  H02M3/07 ,  H02M1/00

Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

公开(公告)号：US20210043251A1

公开(公告)日：2021-02-11

申请号：US17001432

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

IPC: G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

公开(公告)号：US10755771B2

公开(公告)日：2020-08-25

申请号：US16226385

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418 ,  G11C7/22

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.