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公开(公告)号：US12223615B2
公开(公告)日：2025-02-11
申请号：US16917791
申请日：2020-06-30
Applicant: Intel Corporation
Inventor： Vivek De , Ram Krishnamurthy , Amit Agarwal , Steven Hsu , Monodeep Kar
IPC: G06T3/4007 , G06T7/70 , G06T15/06 , G06T17/20
Abstract: A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more voxels having distance values less than the first threshold; and responsively selecting a precise interpolation mode for stepping the ray through the second one or more voxels.
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公开(公告)号：US11411491B2
公开(公告)日：2022-08-09
申请号：US16642853
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.
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3.发明申请公开(公告)号：US20190190725A1
公开(公告)日：2019-06-20
申请号：US15846045
申请日：2017-12-18
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC: H04L9/32
CPC classification number: H04L9/3278
Abstract: An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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公开(公告)号：US20190094897A1
公开(公告)日：2019-03-28
申请号：US15712813
申请日：2017-09-22
Applicant: Intel Corporation
Inventor： Sriram R. Vangal , Turbo Majumder , Vivek De
Abstract: Various embodiments of the invention may be used to find a combination of voltage and frequency that results in a minimum amount of energy consumption in a digital system, including energy consumed by the system's voltage regulator (VR). The process may involve finding a separate point of minimum energy consumption for each of several different modes of the VR, where a mode is the ratio of Vin to Vout for that VR. The smallest value of those points may then be selected as the overall minimum. The process for making this determination may be performed in situ while the device is in operation, and may encompass changes in operational temperature, load, and process variations.
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公开(公告)号：US20190006939A1
公开(公告)日：2019-01-03
申请号：US15638643
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Harish Krishnamurthy , Khondker Ahmed , Vivek De , Nachiket Desai , Suhwan Kim , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram Vangal
Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11940824B2
公开(公告)日：2024-03-26
申请号：US17100603
申请日：2020-11-20
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Harish Krishnamurthy , Krishnan Ravichandran , Vivek De , Scott Chiu , Claudia Patricia Barrera Gonzalez , Jing Han , Rajasekhara Madhusudan Narayana Bhatla
Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.
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公开(公告)号：US11444532B2
公开(公告)日：2022-09-13
申请号：US16727759
申请日：2019-12-26
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Krishnan Ravichandran , Harish Krishnamurthy , Vivek De
Abstract: A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.
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8.发明授权公开(公告)号：US10897364B2
公开(公告)日：2021-01-19
申请号：US15846045
申请日：2017-12-18
Applicant: Intel Corporation
Inventor： Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC: H04L9/32
Abstract: Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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公开(公告)号：US10825511B2
公开(公告)日：2020-11-03
申请号：US16417538
申请日：2019-05-20
Applicant: Intel Corporation
Inventor： Vivek De , Sanu Mathew , Sudhir Satpathy , Vikram Suresh , Raghavan Kumar
IPC: G11C11/419 , H04L9/32 , G09G5/00 , G06F7/58
Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.
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10.发明申请公开(公告)号：US20190317536A1
公开(公告)日：2019-10-17
申请号：US16450873
申请日：2019-06-24
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Harish Krishnamurthy , Krishnan Ravichandran , Vivek De , Scott Chiu , Claudia Patricia Barrera Gonzalez , Jing Han , Rajasekhara Madhusudan Narayana Bhatla
Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.
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