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公开(公告)号：US20230004389A1
公开(公告)日：2023-01-05
申请号：US17358231
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Joseph Williams , Zoran Zivkovic , Jian-Guo Chen , Hong Wan , David Dougherty , Jay O'neill
IPC: G06F9/30
Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.
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公开(公告)号：US11228601B2
公开(公告)日：2022-01-18
申请号：US15926982
申请日：2018-03-20
Applicant: Intel Corporation
Inventor： Zoran Zivkovic , Michael E. Kounavis
IPC: H04L29/06 , H04W12/08 , G07C9/00 , G06F21/35 , G06F21/32 , H04W4/02 , H04L29/08 , G07C9/25 , H04W12/68 , H04W12/122 , G06F21/60 , H04W12/06 , H04W4/40 , G07C9/26 , H04W12/63 , H04W12/79
Abstract: In one embodiment, an apparatus comprises an antenna to receive one or more radio signals, wherein the antenna is associated with a proximity-based access portal. The apparatus further comprises a processor to: detect, based on the one or more radio signals, an access request from a first device, wherein the access request comprises a request to access the proximity-based access portal using an access token associated with an authorized device; determine, based on the one or more radio signals, that the first device is within a particular proximity of the proximity-based access portal; obtain a first motion history associated with movement detected near the proximity-based access portal; obtain a second motion history associated with movement detected by the authorized device; and determine, based on the first motion history and the second motion history, whether the movement detected near the proximity-based access portal matches the movement detected by the authorized device.
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13.发明授权公开(公告)号：US10572982B2
公开(公告)日：2020-02-25
申请号：US15724993
申请日：2017-10-04
Applicant: Intel Corporation
Inventor： Aleksandar Beric , Kari Pulli , Nemanja Jankovic , Zoran Zivkovic
Abstract: Techniques related to image distortion correction for images captured by using a wide-angle lens include homography and a lens distortion correction using a radial-ratio-based look up table.
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14.发明公开公开(公告)号：US20240134818A1
公开(公告)日：2024-04-25
申请号：US18533369
申请日：2023-12-08
Applicant: Intel Corporation
Inventor： Zoran Zivkovic , Jian-Guo Chen , Jay ONeill , Joseph Williams
CPC classification number: G06F15/8007 , G06F1/03
Abstract: Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a look-up table (LUT) in accordance with a fused single instruction stream, multiple data streams (SIMD) instruction. The LUT may contain segment entries that correspond to a result of evaluating a function using a corresponding index values, which represent an independent variable of the function. The index values are used to map data sample values in a data array that is to be interpolated to the segment entries. By using an iterative process of mapping data samples to valid segment entries contained in each LUT portion, the architecture advantageously facilitates scaling to support larger LUTs and thus may be expanded to enable linear interpolation on multiple dimensions.
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15.发明公开公开(公告)号：US20240008045A1
公开(公告)日：2024-01-04
申请号：US17853194
申请日：2022-06-29
Applicant: Intel Corporation
Inventor： Kannan Rajamani , Kameran Azadet , Kevin Kinney , Thomas Smith , Zoran Zivkovic
CPC classification number: H04W72/042 , H04J3/0661
Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.
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Patent Agency Ranking
公开(公告)号：US20230418781A1
公开(公告)日：2023-12-28
申请号：US17851739
申请日：2022-06-28
Applicant: Intel Corporation
Inventor： Kevin Kinney , Zoran Zivkovic
Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.
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公开(公告)号：US20210044761A1
公开(公告)日：2021-02-11
申请号：US16819575
申请日：2020-03-16
Applicant: Intel Corporation
Inventor： Zoran Zivkovic
Abstract: Systems, devices, and techniques related to selecting a key frame for burst image processing are discussed. Such techniques may include generating key frame scores for at least some frames of a multi-frame burst image capture such that the key frame scores include a combination of an image quality component, a shutter lag component, and a burst image processing latency component and selecting a frame having a maximum key frame score as the key frame.
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公开(公告)号：US10796200B2
公开(公告)日：2020-10-06
申请号：US15965158
申请日：2018-04-27
Applicant: Intel Corporation
Inventor： Aleksandar Sutic , Zoran Zivkovic , Gilad Michael
Abstract: In an example method for training image signal processors, a reconstructed image is generated via an image signal processor based on a sensor image. An intermediate loss function is generated based on a comparison of an output of one or more corresponding layers of a computer vision network and a copy of the computer vision network. The output of the computer vision network is based on the reconstructed image. An image signal processor is trained based on the intermediate loss function.
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公开(公告)号：US20190050682A1
公开(公告)日：2019-02-14
申请号：US15965158
申请日：2018-04-27
Applicant: Intel Corporation
Inventor： Aleksandar Sutic , Zoran Zivkovic , Gilad Michael
Abstract: In an example method for training image signal processors, a reconstructed image is generated via an image signal processor based on a sensor image. An intermediate loss function is generated based on a comparison of an output of one or more corresponding layers of a computer vision network and a copy of the computer vision network. The output of the computer vision network is based on the reconstructed image. An image signal processor is trained based on the intermediate loss function.
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公开(公告)号：US20180095877A1
公开(公告)日：2018-04-05
申请号：US15281288
申请日：2016-09-30
Applicant: INTEL CORPORATION
Inventor： Aleksandar Beric , Zoran Zivkovic
IPC: G06F12/0802 , G06K9/00
CPC classification number: G06F12/0802 , G06F2212/301 , G06K9/00 , G06K9/00221 , G06K9/00986
Abstract: An example apparatus for processing scattered data includes an address buffer to receive a plurality of vector addresses corresponding to input vector data comprising scattered samples to be processed. The apparatus also includes a multi-bank memory to receive the input vector data and send output vector data. The apparatus further includes a memory controller comprising an address scheduler to assign an address to each bank of the multi-bank memory.
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