中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

153 records (took 0.021 seconds)

    EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY TOP ELECTRODE STRUCTURE
    12.
    发明公开
    EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY TOP ELECTRODE STRUCTURE 审中-公开

    公开(公告)号：US20230157181A1

    公开(公告)日：2023-05-18

    申请号：US17455226

    申请日：2021-11-17

    Applicant: International Business Machines Corporation

    Inventor： Ashim Dutta ,  Chih-Chao Yang

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

    CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

    Abstract: An approach to provide a pillar-type memory device with a bump of a conductive material on a top electrode of the pillar-type memory device. The top electrode is composed of a thin layer of the top electrode material. The bump of the conductive material increases the height of the top electrode after pillar formation for the pillar-type memory device. The pillar-type memory device includes the bump of the conductive material with a semi-sphere-like bump of the conductive metal that is slightly wider than the top electrode of the pillar-type memory device. A contact connects with the bump of the conductive material on the top electrode.

    AIRGAP ISOLATION FOR BACK-END-OF-THE-LINE SEMICONDUCTOR INTERCONNECT STRUCTURE WITH TOP VIA
    13.
    发明申请
    AIRGAP ISOLATION FOR BACK-END-OF-THE-LINE SEMICONDUCTOR INTERCONNECT STRUCTURE WITH TOP VIA 有权

    公开(公告)号：US20230099965A1

    公开(公告)日：2023-03-30

    申请号：US17449381

    申请日：2021-09-29

    Applicant: International Business Machines Corporation

    Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Praveen Joseph ,  Jennifer Church

    IPC: H01L23/532 ,  H01L21/768

    Abstract: Airgap isolation for back-end-of-the-line interconnect structures includes a dielectric liner formed above a top surface and opposite sidewalls of each of a plurality of metal lines on a substrate, the dielectric liner disposed above a top surface of the substrate not covered by the plurality of metal lines, portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines are separated by a space. A dielectric cap is disposed above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between adjacent metal lines.

    DECOUPLED INTERCONNECT STRUCTURES
    16.
    发明申请
    DECOUPLED INTERCONNECT STRUCTURES 有权

    公开(公告)号：US20230081953A1

    公开(公告)日：2023-03-16

    申请号：US17447586

    申请日：2021-09-14

    Applicant: International Business Machines Corporation

    Inventor： Saumya Sharma ,  Ashim Dutta ,  Tianji Zhou ,  Chih-Chao Yang

    IPC: H01L23/528 ,  H01L21/768

    Abstract: A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.

    Footing flare pedestal structure
    18.
    发明授权
    Footing flare pedestal structure 有权

    公开(公告)号：US11302639B2

    公开(公告)日：2022-04-12

    申请号：US16744960

    申请日：2020-01-16

    Applicant: International Business Machines Corporation

    Inventor： Chih-Chao Yang ,  Baozhen Li ,  Ashim Dutta

    IPC: H01L23/532 ,  H01L23/522 ,  H01L43/08 ,  H01L27/11597 ,  H01L45/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L27/24

    Abstract: Re-depositing of metal-containing particles of an embedded electrically conductive structure onto sidewalls of an overlying metal-containing structure is alleviated in the present application by providing a pedestal structure between the embedded electrically conductive structure and the metal-containing structure, wherein the pedestal structure has a flared sidewall that extends beyond a perimeter of the embedded electrically conductive structure. Such a pedestal structure (which can be referred to herein as a footing flare pedestal structure) mitigates, and in some embodiments, entirely eliminates, the exposure of the embedded electrically conductive structure during the patterning of metal-containing layers formed atop the embedded electrically conductive structure.

    Self-aligned top vias over metal lines formed by a damascene process
    19.
    发明授权
    Self-aligned top vias over metal lines formed by a damascene process 有权

    公开(公告)号：US11189527B2

    公开(公告)日：2021-11-30

    申请号：US16826944

    申请日：2020-03-23

    Applicant: International Business Machines Corporation

    Inventor： Timothy Mathew Philip ,  Sagarika Mukesh ,  Dominik Metzler ,  Ashim Dutta ,  John Christopher Arnold

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

    Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer walls on the opposed vertical walls of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.

    Inverse tone pillar printing method using polymer brush grafts
    20.
    发明授权
    Inverse tone pillar printing method using polymer brush grafts 有权

    公开(公告)号：US11133195B2

    公开(公告)日：2021-09-28

    申请号：US16400003

    申请日：2019-04-30

    Applicant: International Business Machines Corporation

    Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Praveen Joseph ,  Ashim Dutta

    IPC: H01L21/308 ,  H01L21/033

    Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

Patent Agency Ranking