公开(公告)号：US20180219011A1

公开(公告)日：2018-08-02

申请号：US15937006

申请日：2018-03-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768

CPC classification number: H01L22/22 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20180122714A1

公开(公告)日：2018-05-03

申请号：US15848151

申请日：2017-12-20

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L21/66 ,  H01L21/683 ,  H01L27/12 ,  H01L23/50 ,  H01L21/84 ,  H01L23/528

CPC classification number: H01L27/0924 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L22/22 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20170309631A1

公开(公告)日：2017-10-26

申请号：US15617472

申请日：2017-06-08

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L22/22 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20190363083A1

公开(公告)日：2019-11-28

申请号：US15985864

申请日：2018-05-22

Applicant: International Business Machines Corporation

Inventor： Xin MIAO ,  Chen ZHANG ,  Kangguo CHENG ,  Wenyu XU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8258

Abstract: A method and structure for forming hybrid high mobility channel transistors. The method includes: providing a substrate, epitaxially growing a buffer layer over the substrate and a semiconductor layer over the buffer layer, forming a partial opening over the semiconductor layer, epitaxially growing a second semiconductor layer in the opening, forming a first plurality of fins from the first semiconductor layer and a second plurality of fins from the second semiconductor layer, where the first semiconductor layer and the second semiconductor material comprise different materials, oxidizing a portion of the second plurality of fins, and stripping the oxidized portion of the second plurality of fins, where after striping the oxidized portion of the second plurality of fins, the second plurality of fins have the same width as the first plurality of fins.

公开(公告)号：US20190341452A1

公开(公告)日：2019-11-07

申请号：US15971529

申请日：2018-05-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin MIAO ,  Chen ZHANG ,  Kangguo CHENG ,  Wenyu XU

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02

Abstract: A technique relates to a semiconductor device. A stack is formed of alternating layers of inserted layers and channel layers on a substrate. Source or drain (S/D) regions are formed on opposite sides of the stack. The inserted layers are converted into oxide layers. Gate materials are formed on the stack.

公开(公告)号：US20170352742A1

公开(公告)日：2017-12-07

申请号：US15171040

申请日：2016-06-02

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/417 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/02609 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

公开(公告)号：US20170309630A1

公开(公告)日：2017-10-26

申请号：US15137036

申请日：2016-04-25

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L22/22 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20170309527A1

公开(公告)日：2017-10-26

申请号：US15497608

申请日：2017-04-26

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L21/66 ,  H01L21/84 ,  H01L21/683 ,  H01L23/50 ,  H01L23/528 ,  H01L27/12

CPC classification number: H01L27/0924 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L22/22 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20230031574A1

公开(公告)日：2023-02-02

申请号：US17388572

申请日：2021-07-29

Applicant: International Business Machines Corporation

Inventor： Ruilong XIE ,  Chen ZHANG ,  Julien FROUGIER ,  Alexander REZNICEK ,  Shogo MOCHIZUKI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

公开(公告)号：US20200381300A1

公开(公告)日：2020-12-03

申请号：US16425133

申请日：2019-05-29

Applicant: International Business Machines Corporation

Inventor： Chen ZHANG ,  Heng WU ,  Kangguo CHENG ,  Tenko YAMASHITA

IPC: H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L23/48

Abstract: A stacked semiconductor device structure and method for fabricating the same. The stacked semiconductor device structure includes a first vertical transport field effect transistor (VTFET) and a second VTFET stacked on the first VTFET. The structure further includes at least one power line and at least one ground line disposed within a backside of the stacked semiconductor structure. The method includes at least orientating a structure including a first VTFET and a second VTFET stacked on the first VTFET such that a multi-layer substrate, on which the first VTFET is formed, is above the first and second VTFETs. First and second contact trenches are formed through at least one layer of the multi-layer substrate. The first contact trench exposes a portion of a metal contact and the second contact trench exposes a portion of a source/drain region. The first and second contact trenches are filled with a contact material.