公开(公告)号：US20230307296A1

公开(公告)日：2023-09-28

申请号：US17656174

申请日：2022-03-23

Applicant: International Business Machines Corporation

Inventor： Ruilong XIE ,  Chen ZHANG ,  Heng WU ,  Julien FROUGIER ,  Alexander REZNICEK

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L29/0649 ,  H01L29/41725 ,  H01L21/76802 ,  H01L21/76847

Abstract: A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired connection from a top of the stacked FET to the buried components. The buried interconnect allows for efficient scaling of the stacked devices without extraneous wiring from a top of the device to each epitaxial region/device within the overall device.

公开(公告)号：US20180114849A1

公开(公告)日：2018-04-26

申请号：US15838456

申请日：2017-12-12

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

公开(公告)号：US20170352743A1

公开(公告)日：2017-12-07

申请号：US15617573

申请日：2017-06-08

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/417 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/02609 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

公开(公告)号：US20210233996A1

公开(公告)日：2021-07-29

申请号：US17208622

申请日：2021-03-22

Applicant: International Business Machines Corporation

Inventor： Chen ZHANG ,  Peng XU ,  Chun Wing YEUNG

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

公开(公告)号：US20200343241A1

公开(公告)日：2020-10-29

申请号：US16395563

申请日：2019-04-26

Applicant: International Business Machines Corporation

Inventor： Heng WU ,  Chen ZHANG ,  Kangguo CHENG ,  Tenko YAMASHITA ,  Joshua M. RUBIN

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

公开(公告)号：US20190318963A1

公开(公告)日：2019-10-17

申请号：US15951355

申请日：2018-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin MIAO ,  Kangguo CHENG ,  Chen ZHANG ,  Wenyu XU

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

公开(公告)号：US20190189739A1

公开(公告)日：2019-06-20

申请号：US15844725

申请日：2017-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao LI ,  Kangguo CHENG ,  Chen ZHANG ,  Xin MIAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/161

Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.

公开(公告)号：US20230178549A1

公开(公告)日：2023-06-08

申请号：US17643362

申请日：2021-12-08

Applicant: International Business Machines Corporation

Inventor： Sung Dae SUK ,  Timothy Mathew PHILIP ,  Junli WANG ,  Dechao GUO ,  Chen ZHANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L23/5286 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/66545

Abstract: Stacked field effect transistors are provided such having a first power rail; a second power rail; a first Field Effect Transistor (FET) having a first gate connected to the first power rail; a second FET having a second gate connected to the second power rail; and an insulator separating the first FET from the second FET, wherein the first power rail, the second power rail, the first FET, and the second FET are aligned on a shared axis, and wherein the first power rail and the second power rail are located on opposite sides of the device.

公开(公告)号：US20210280578A1

公开(公告)日：2021-09-09

申请号：US17321563

申请日：2021-05-17

Applicant: International Business Machines Corporation

Inventor： Heng WU ,  Chen ZHANG ,  Kangguo CHENG ,  Tenko YAMASHITA ,  Joshua M. RUBIN

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

公开(公告)号：US20200176335A1

公开(公告)日：2020-06-04

申请号：US16781183

申请日：2020-02-04

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L21/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/786 ,  H01L21/683 ,  H01L21/84 ,  H01L23/50 ,  H01L23/528 ,  H01L27/12 ,  H01L21/8238

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.