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    LITHOGRAPHY PROCESS MONITORING OF LOCAL INTERCONNECT CONTINUITY
    2.
    发明申请
    LITHOGRAPHY PROCESS MONITORING OF LOCAL INTERCONNECT CONTINUITY 有权
    本地互连连续性的地震过程监测

    公开(公告)号：US20140361298A1

    公开(公告)日：2014-12-11

    申请号：US13913007

    申请日：2013-06-07

    Applicant: GLOBAL FOUNDRIES, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hyun-Jin CHO ,  Tenko YAMASHITA ,  Chun-chen YEH ,  Hui ZANG

    IPC: H01L21/66

    CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/34

    Abstract: Disclosed is a novel system and method to form local interconnects in a continuity test structure. The method begins with a first set of transistor gate lines and a second set of transistor gate lines are formed. Next, a first group of two or more local interconnect lines landing on transistor gates and formed substantially perpendicular to the first set of transistor gate lines and electrically coupled therewith is formed using a first lithography pass. A second group of two or more local interconnect lines landing and formed substantially perpendicular to the second set of transistor gate lines and electrically coupled therewith is formed during second lithography pass. For some technologies, a third set of transistor gate lines is formed along with a third group using a third lithography pass.

    Abstract translation: 公开了一种在连续性测试结构中形成局部互连的新型系统和方法。 该方法由第一组晶体管栅极线开始，并且形成第二组晶体管栅极线。 接下来，使用第一光刻通道形成第一组两个或更多个局部互连线，其位于晶体管栅极上并且基本上垂直于第一组晶体管栅极线形成并与之电耦合的局部互连线。 在第二光刻通过期间形成第二组两个或更多个局部互连线，其基本垂直于第二组晶体管栅极线并与之电耦合。 对于一些技术，使用第三光刻通道与第三组一起形成第三组晶体管栅极线。

    FORMING STRAINED AND RELAXED SILICON AND SILICON GERMANIUM FINS ON THE SAME WAFER
    3.
    发明申请
    FORMING STRAINED AND RELAXED SILICON AND SILICON GERMANIUM FINS ON THE SAME WAFER 有权
    在同一波长处形成应变和放松的硅和硅锗

    公开(公告)号：US20140264595A1

    公开(公告)日：2014-09-18

    申请号：US13828283

    申请日：2013-03-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Veeraraghavan S. BASKER ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Tenko YAMASHITA ,  Chun-chen YEH

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785 ,  H01L29/7855

    Abstract: Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon.

    Abstract translation: 各种实施例在半导体晶片上形成应变和松弛的硅和锗锗翅片。 在一个实施例中，形成半导体晶片。 半导体晶片包括衬底，电介质层和应变硅锗（SiGe）层。 应变SiGe层的至少一个区域被转化为松弛的SiGe区域。 至少一个应变SiGe鳍由应变SiGe层的第一应变SiGe区形成。 从弛豫SiGe区域的第一部分形成至少一个松弛的SiGe鳍。 在应变SiGe层的第二应变SiGe区域外延生长弛豫硅。 应变硅在弛豫SiGe区域的第二部分外延生长。 从松散的硅形成至少一个松散的硅散热片。 从应变硅形成至少一个应变硅翅片。

    Preventing FIN Erosion and Limiting Epi Overburden in FinFET Structures by Composite Hardmask
    4.
    发明申请
    Preventing FIN Erosion and Limiting Epi Overburden in FinFET Structures by Composite Hardmask 有权
    通过复合硬掩模防止FinFET结构中的FIN侵蚀和限制Epi覆盖

    公开(公告)号：US20140159166A1

    公开(公告)日：2014-06-12

    申请号：US13708126

    申请日：2012-12-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Veeraraghavan S. BASKER ,  Effendi LEOBANDUNG ,  Tenko YAMASHITA ,  Chun-chen YEH

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged.

    Abstract translation: 通过在绝缘层上包含含硅层的基板上形成硬掩模层来形成FinFET结构。 硬掩模层包括含硅层上的第一层，第二层和第三层。 翅片阵列由硬掩模层和含硅层形成。 形成盖子，其覆盖翅片阵列中的每一个的一部分而不是全部长度。 该部分覆盖阵列中的每个翅片。 门限定栅极两侧的源/漏区。 隔离件形成在栅极的每一侧上，形成间隔物以进行以从源极/漏极区域中的鳍片的部分去除第三层。 硬掩模层的第二层从源极/漏极区域中的鳍片的部分去除，并且源极/漏极区域中的鳍片被合并。

    FORMATION OF STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS
    5.
    发明申请
    FORMATION OF STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20200343222A1

    公开(公告)日：2020-10-29

    申请号：US16395546

    申请日：2019-04-26

    Applicant: International Business Machines Corporation

    Inventor： Heng WU ,  Gen TSUTSUI ,  Tenko YAMASHITA

    IPC: H01L25/065 ,  H01L25/00 ,  H01L25/07 ,  H01L21/762

    Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising a first semiconductor fin and a second VTFET stacked on the first VTFET. The second VTFET includes a second semiconductor fin that is separate and distinct from the first semiconductor fin. At least one insulating layer is disposed on a top surface of the first VTFET. The second VTFET is disposed on the at least one insulating layer. The method includes forming a first vertical VTFET on a first substrate and bonding a second substrate to and on top of the first VTFET. A second VTFET is formed on the second substrate.

    MIRROR CONTACT CAPACITOR
    6.
    发明申请
    MIRROR CONTACT CAPACITOR 有权

    公开(公告)号：US20170373070A1

    公开(公告)日：2017-12-28

    申请号：US15192121

    申请日：2016-06-24

    Applicant: International Business Machines Corporation

    Inventor： Terence B. HOOK ,  Joshua M. RUBIN ,  Tenko YAMASHITA

    IPC: H01L27/108 ,  H01L29/06

    CPC classification number: H01L27/10829 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/0649

    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top surface of the substrate. At least one transistor contacts the bonding layer. The transistor includes at least one gate structure disposed on and in contact with a bottom surface of a semiconductor layer of the transistor. The semiconductor further includes a capacitor disposed adjacent to the transistor. The capacitor contacts the semiconductor layer of the transistor and extends down into the substrate. The method includes forming at least one transistor and then flipping the transistor. After the transistor has been flipped, the transistor is bonded to a new substrate. An initial substrate of the transistor is removed to expose a semiconductor layer. A capacitor is formed adjacent to the transistor and contacts with the semiconductor layer. A contact node is formed adjacent to the capacitor.

    STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER
    7.
    发明申请
    STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER 有权
    在同一波长上的应变硅纳米管和硅锗管

    公开(公告)号：US20140264755A1

    公开(公告)日：2014-09-18

    申请号：US13800984

    申请日：2013-03-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Veeraraghavan S. BASKER ,  Chun-chen YEH ,  Tenko YAMASHITA

    IPC: H01L29/16 ,  H01L21/02

    CPC classification number: H01L27/1211 ,  H01L21/02107 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0337 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  Y10S438/933

    Abstract: Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer.

    Abstract translation: 各种实施例在半导体晶片上形成硅和硅锗散热片。 在一个实施例中，获得半导体晶片。 半导体晶片包括衬底，电介质层和包括硅锗（SiGe）的半导体层。 至少一个SiGe鳍从半导体晶片的至少一个PFET区域中的半导体层的至少第一SiGe区形成。 应变硅在半导体层的至少第二SiGe区域外延生长。 在半导体晶片的至少一个NFET区域中，应变硅形成至少一个应变硅散热片。

    BURIED POWER AND GROUND IN STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS
    9.
    发明申请
    BURIED POWER AND GROUND IN STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20200381300A1

    公开(公告)日：2020-12-03

    申请号：US16425133

    申请日：2019-05-29

    Applicant: International Business Machines Corporation

    Inventor： Chen ZHANG ,  Heng WU ,  Kangguo CHENG ,  Tenko YAMASHITA

    IPC: H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L23/48

    Abstract: A stacked semiconductor device structure and method for fabricating the same. The stacked semiconductor device structure includes a first vertical transport field effect transistor (VTFET) and a second VTFET stacked on the first VTFET. The structure further includes at least one power line and at least one ground line disposed within a backside of the stacked semiconductor structure. The method includes at least orientating a structure including a first VTFET and a second VTFET stacked on the first VTFET such that a multi-layer substrate, on which the first VTFET is formed, is above the first and second VTFETs. First and second contact trenches are formed through at least one layer of the multi-layer substrate. The first contact trench exposes a portion of a metal contact and the second contact trench exposes a portion of a source/drain region. The first and second contact trenches are filled with a contact material.

    MIRROR CONTACT CAPACITOR
    10.
    发明申请
    MIRROR CONTACT CAPACITOR 审中-公开

    公开(公告)号：US20180102367A1

    公开(公告)日：2018-04-12

    申请号：US15838496

    申请日：2017-12-12

    Applicant: International Business Machines Corporation

    Inventor： Terence B. HOOK ,  Joshua M. RUBIN ,  Tenko YAMASHITA

    IPC: H01L27/108 ,  H01L29/06

    CPC classification number: H01L27/10829 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/0649

    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top surface of the substrate. At least one transistor contacts the bonding layer. The transistor includes at least one gate structure disposed on and in contact with a bottom surface of a semiconductor layer of the transistor. The semiconductor further includes a capacitor disposed adjacent to the transistor. The capacitor contacts the semiconductor layer of the transistor and extends down into the substrate. The method includes forming at least one transistor and then flipping the transistor. After the transistor has been flipped, the transistor is bonded to a new substrate. An initial substrate of the transistor is removed to expose a semiconductor layer. A capacitor is formed adjacent to the transistor and contacts with the semiconductor layer. A contact node is formed adjacent to the capacitor.

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