公开(公告)号：US20220013986A1

公开(公告)日：2022-01-13

申请号：US17484180

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Julien FROUGIER ,  Kangguo CHENG ,  Ruilong Xie ,  Chanro PARK

IPC: H01S5/10 ,  H01S5/062

Abstract: A device and a method to produce an augmented-laser (ATLAS) comprising a bi-stable resistive system (BRS) integrated in series with a semiconductor laser. The laser exhibits reduction/inhibition of the Spontaneous Emission (SE) below lasing threshold by leveraging the abrupt resistance switch of the BRS. The laser system comprises a semiconductor laser and a BRS operating as a reversible switch. The BRS operates in a high resistive state in which a semiconductor laser is below a lasing threshold and emitting in a reduced spontaneous emission regime, and a low resistive state in which a semiconductor laser is above or equal to a lasing threshold and emitting in a stimulated emission regime. The BRS operating as a reversible switch is electrically connected in series across two independent chips or on a single wafer. The BRS is formed using insulator-to-metal transition (IMT) materials or is formed using threshold-switching selectors (TSS).

公开(公告)号：US20210135108A1

公开(公告)日：2021-05-06

申请号：US16670215

申请日：2019-10-31

Applicant: International Business Machines Corporation

Inventor： Chanro PARK ,  Kangguo CHENG ,  Ruilong Xie ,  Choonghyun LEE

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The method includes forming a sacrificial layer over a transistor drain contact; forming a first dielectric layer over the sacrificial layer; forming a cell contact hole through the first dielectric layer; forming an access contact hole through the first dielectric layer and exposing the sacrificial layer; removing the sacrificial layer thereby forming a cavity connecting a bottom opening of the cell contact hole and a bottom opening of the access contact hole; forming by atomic layer deposition in the cell contact hole a second dielectric layer including a seam; forming a bottom electrode within the cavity and in contact with the drain contact, the second dielectric layer, and the seam; and forming a top electrode over the first dielectric layer and in contact with the second dielectric layer and the seam.

公开(公告)号：US20200343241A1

公开(公告)日：2020-10-29

申请号：US16395563

申请日：2019-04-26

Applicant: International Business Machines Corporation

Inventor： Heng WU ,  Chen ZHANG ,  Kangguo CHENG ,  Tenko YAMASHITA ,  Joshua M. RUBIN

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

公开(公告)号：US20200161303A1

公开(公告)日：2020-05-21

申请号：US16691732

申请日：2019-11-22

Applicant: International Business Machines Corporation

Inventor： ZHENXING BI ,  Kangguo CHENG ,  ZHENG XU ,  DEXIN KONG

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/08 ,  H01L29/66

Abstract: An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.

公开(公告)号：US20200161302A1

公开(公告)日：2020-05-21

申请号：US16192896

申请日：2018-11-16

Applicant: International Business Machines Corporation

Inventor： ZHENXING BI ,  Kangguo CHENG ,  ZHENG XU ,  DEXIN KONG

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/033 ,  H01L21/8238

Abstract: An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.

公开(公告)号：US20200091314A1

公开(公告)日：2020-03-19

申请号：US16668496

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L29/49 ,  H01L23/485 ,  H01L29/417 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78

Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.

公开(公告)号：US20190318963A1

公开(公告)日：2019-10-17

申请号：US15951355

申请日：2018-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin MIAO ,  Kangguo CHENG ,  Chen ZHANG ,  Wenyu XU

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

公开(公告)号：US20190214481A1

公开(公告)日：2019-07-11

申请号：US15865383

申请日：2018-01-09

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Peng XU

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L27/12 ,  H01L21/265 ,  H01L29/78

Abstract: Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source/drain region layer and source/drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source/drain contact. The source/drain contact is disposed directly on and contacting the entire source/drain region layer, and at a vertical level thereabove, the source/drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source/drain region layer. A method uses a reverse contact mask to form a shape of the source/drain contact into an inverted “T” shape.

公开(公告)号：US20190214456A1

公开(公告)日：2019-07-11

申请号：US16359292

申请日：2019-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Christopher J. PENNY ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L28/88 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53228 ,  H01L28/60 ,  H01L28/82

Abstract: Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

公开(公告)号：US20190189739A1

公开(公告)日：2019-06-20

申请号：US15844725

申请日：2017-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao LI ,  Kangguo CHENG ,  Chen ZHANG ,  Xin MIAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/161

Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.