公开(公告)号：US20230360971A1

公开(公告)日：2023-11-09

申请号：US17662436

申请日：2022-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Albert M. Chu ,  Albert M. Young ,  Junli Wang ,  Brent A. Anderson

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/417

CPC classification number: H01L21/76895 ,  H01L23/481 ,  H01L21/76897 ,  H01L29/41775 ,  H01L24/32

Abstract: Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.

公开(公告)号：US20230299205A1

公开(公告)日：2023-09-21

申请号：US17655371

申请日：2022-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Julien Frougier ,  Ruilong Xie ,  Chen Zhang

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78618

Abstract: A semiconductor structure including a bottom source drain region arranged above front-end-of-line circuitry, a gate region disposed above and insulated from the bottom source drain region, a top source drain region disposed above and insulated from the gate region, and a channel region adjacent to the gate region and extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.

公开(公告)号：US20230298646A1

公开(公告)日：2023-09-21

申请号：US17655569

申请日：2022-03-21

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Dimitri Houssameddine

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L27/222

Abstract: An approach for providing a semiconductor structure for a stacked magnetoresistive random-access memory (MRAM) device that includes a first magnetic tunnel junction on a bottom electrode and at least one second magnetic tunnel junction above the first magnetic tunnel junction. The semiconductor structure includes the first magnetic tunnel junction is a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction of a voltage-controlled magnetic anisotropy (VCMA) MRAM device. The VCMA-MRAM device is composed of a first reference layer, a first tunnel barrier layer, and a first free layer. The semiconductor structure includes the second magnetic tunnel junction that is a spin-transfer torque (STT) magnetic tunnel junction of a STT-MRAM device. The STT-MRAM device is composed of a second reference layer, a second tunnel barrier layer, and a second free layer where the STT magnetic tunnel junction has a smaller cross-sectional area than the VCMA magnetic tunnel junction (MTJ).

公开(公告)号：US20230180623A1

公开(公告)日：2023-06-08

申请号：US17545485

申请日：2021-12-08

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Pouya Hashemi ,  Ruilong Xie ,  Julien Frougier

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A method of manufacturing an MRAM device includes forming an MTJ stack on a substrate, forming a hardmask layer on the MTJ stack, forming etch pattern pads on the hardmask, forming a spacer on the sides of the etch pattern pads to form first openings exposing the hardmask, patterning the MTJ stack by a first etch using the first openings to form a plurality of first MTJ pillars separated by first vias, filling the first vias with a first dielectric, removing the spacers from the etch pattern pads to form a plurality of second openings between the first dielectric and the etch pattern pads, patterning the plurality of first MTJ pillars by a second etch using the second openings to form a plurality of second MTJ pillars separated by second vias and filling the second vias with a second dielectric to encapsulate the plurality of second MTJ pillars.

公开(公告)号：US20230178559A1

公开(公告)日：2023-06-08

申请号：US17541529

申请日：2021-12-03

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Heng Wu ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/1222 ,  H01L27/092 ,  H01L29/42392 ,  H01L27/1262 ,  H01L21/823878

Abstract: Fork sheet FET devices with airgap isolation are provided. In one aspect, a fork sheet FET device includes: at least a first nanosheet FET and a second nanosheet FET; and a dielectric pillar disposed directly between the first nanosheet FET and the second nanosheet FET, wherein the dielectric pillar includes an airgap. For instance, the first nanosheet FET and the second nanosheet FET can have nanosheets that extend horizontally on opposite sides of the dielectric pillar. A method of forming a fork sheet FET device having airgap isolation is also provided.

公开(公告)号：US20230163126A1

公开(公告)日：2023-05-25

申请号：US17455935

申请日：2021-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Heng Wu ,  Alexander Reznicek ,  Oleg Gluschenkov

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823871 ,  H01L29/66742

Abstract: A semiconductor device comprising a first channel region located on a substrate and a second channel region located on the substrate. A metal gate that extends across the first channel to the second channel and an air gap located in the metal gate, wherein the air gap is located between the first channel region and the second channel region, wherein the metal gate is located on top of the air gap.

公开(公告)号：US20230116251A1

公开(公告)日：2023-04-13

申请号：US17489029

申请日：2021-09-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Alexander Reznicek ,  Ruilong Xie ,  Julien Frougier ,  Chen Zhang

IPC: G06N3/063

Abstract: A semiconductor structure is provided. The semiconductor device includes a magnetic layer located between a first electrode and a second electrode formed on a substrate. The semiconductor device further includes a first write element electrically coupled to the magnetic layer adjacent to the first electrode. The semiconductor device also includes a second write element electrically coupled to the magnetic layer adjacent to the second electrode. The semiconductor device additionally includes a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element.

公开(公告)号：US11616140B2

公开(公告)日：2023-03-28

申请号：US17225327

申请日：2021-04-08

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Gen Tsutsui ,  Lan Yu ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A vertical field effect transistor structure having at least two vertically oriented fins extending from a substrate. The vertical field effect transistor structure further includes a first source/drain region disposed in the substrate between the two vertically oriented fins and under each of the fins. The outer ends of the first source/drain region are in contact with outer ends of the fins. A portion of the first source/drain region extends beyond the fins.

公开(公告)号：US20230081603A1

公开(公告)日：2023-03-16

申请号：US17473359

申请日：2021-09-13

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Tian Shen ,  Kevin W. Brew ,  Jingyun Zhang

IPC: H01L45/00

Abstract: A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

公开(公告)号：US20230068802A1

公开(公告)日：2023-03-02

申请号：US17410499

申请日：2021-08-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wei Wang ,  Ruilong Xie ,  Alexander Reznicek ,  Heng Wu

IPC: H01L27/105

Abstract: A high bandwidth memory is provided. The high bandwidth memory includes a region of dynamic random access memory devices, a region of non-volatile memory devices adjacent to the region of dynamic random access memory devices, and a region of logic devices adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices.