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    SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS
    12.
    发明申请
    SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS 审中-公开

    公开(公告)号：US20190102505A1

    公开(公告)日：2019-04-04

    申请号：US15719698

    申请日：2017-09-29

    Applicant: International Business Machines Corporation

    Inventor： Jean Audet ,  Franklin M. Baez ,  Jason L. Frankel ,  Paul R. Walling

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/40

    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.

    Flip chip assembly with connected component
    13.
    发明授权
    Flip chip assembly with connected component 有权

    公开(公告)号：US10211174B2

    公开(公告)日：2019-02-19

    申请号：US15396844

    申请日：2017-01-03

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jean Audet ,  Luc G. Guerin ,  Richard Langlois ,  Stephan L. Martel ,  Sylvain E. Ouimet

    IPC: H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H01L49/02

    Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.

    INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES
    15.
    发明申请
    INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES 审中-公开
    具有施工结构和嵌入式导电金属结构的间隔器

    公开(公告)号：US20160372337A1

    公开(公告)日：2016-12-22

    申请号：US15255244

    申请日：2016-09-02

    Applicant: International Business Machines Corporation

    Inventor： Jean Audet ,  Benjamin V. Fasano ,  Shidong Li

    IPC: H01L21/48 ,  H01L21/027 ,  H01L25/065 ,  H01L23/498 ,  H01L23/15

    CPC classification number: H01L21/486 ,  H01L21/0274 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.

    Abstract translation: 在非硅插入器基板中形成晶格结构，以产生作为电介质场的岛的通孔间距的倍数的大电池。 然后用电介质材料填充每个单元电池。 此后，在电池中的电介质材料内产生孔（即通孔或盲孔）。 在孔形成之后，导电金属形成在提供插入件的每个孔中。 这种方法可以实现基于有机材料的精细间距处理，将热膨胀系数（TCE）应力从金属过孔隔离到低TCE载体，并以面板形式形成高容量，低成本组件的路径。

    Interposer with lattice construction and embedded conductive metal structures
    16.
    发明授权
    Interposer with lattice construction and embedded conductive metal structures 有权
    插入式晶格结构和嵌入式导电金属结构

    公开(公告)号：US09443799B2

    公开(公告)日：2016-09-13

    申请号：US14571352

    申请日：2014-12-16

    Applicant: International Business Machines Corporation

    Inventor： Jean Audet ,  Benjamin V. Fasano ,  Shidong Li

    IPC: H01L21/56 ,  H01L21/48 ,  H01L23/15 ,  H01L23/522 ,  H01L23/498

    CPC classification number: H01L21/486 ,  H01L21/0274 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.

    Abstract translation: 在非硅插入器基板中形成晶格结构，以产生作为电介质场的岛的通孔间距的倍数的大电池。 然后用电介质材料填充每个单元电池。 此后，在电池中的电介质材料内产生孔（即通孔或盲孔）。 在孔形成之后，导电金属形成在提供插入件的每个孔中。 这种方法可以实现基于有机材料的精细间距处理，将热膨胀系数（TCE）应力从金属过孔隔离到低TCE载体，并以面板形式形成高容量，低成本组件的路径。

    Multi terminal capacitor within input output path of semiconductor package interconnect
    20.
    发明授权
    Multi terminal capacitor within input output path of semiconductor package interconnect 有权

    公开(公告)号：US10224274B2

    公开(公告)日：2019-03-05

    申请号：US15796782

    申请日：2017-10-28

    Applicant: International Business Machines Corporation

    Inventor： Charles L. Arvin ,  Jean Audet ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Brian R. Sundlof

    IPC: H01L23/00 ,  H01L23/50 ,  H01L25/18 ,  H01L23/367 ,  H01L23/498 ,  H01L23/522

    Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.

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