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公开(公告)号:US10892643B2
公开(公告)日:2021-01-12
申请号:US15920803
申请日:2018-03-14
Applicant: International Business Machines Corporation
Inventor: Bing Dang , Duixian Liu , Jean-Olivier Plouchart , John Knickerbocker
IPC: H02J50/00 , H04B1/3827 , H02J50/10 , H02J50/80 , H02J50/90 , H02J50/40 , A61L2/26 , A61L2/10 , A61L2/04 , A61L2/16
Abstract: Systems, devices, and techniques facilitating wirelessly charging and/or communicating with one or more electronic devices (e.g., electronic wearable devices) are provided. A device can comprise a memory and a storage component that can be operatively coupled to the memory. The storage component can comprise one or more recesses that can receive a second device that can be charged by the storage component. The storage component can comprise a charging circuit and an inductive circuit that can be coupled to the charging circuit. The storage component can harvest energy from one or more energy sources to charge the charging circuit. Based on the energy harvested, the inductive circuit can inductively couple to the second device having a second inductive circuit and positioned in at least one of the recesses and the inductive circuit can charge a power source of the second device.
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公开(公告)号:US10605741B2
公开(公告)日:2020-03-31
申请号:US16022282
申请日:2018-06-28
Applicant: International Business Machines Corporation
Inventor: Minhua Lu , Vince Siu , Russell Budd , Evan Colgan , John Knickerbocker
Abstract: Techniques for colorimetric based test strip analysis and reader system are provided. In one aspect, a method of test strip analysis includes: illuminating a test strip wetted with a sample with select spectrums of light, wherein the test strip includes test pads that are configured to change color in the presence of an analyte in the sample; obtaining at least one digital image of the test strip; and analyzing color intensity from the at least one digital image against calibration curves to determine an analyte concentration in the sample with correction for one or more interference substances in the sample that affect the color intensity. A calibration method and a reader device are also provided.
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公开(公告)号:US11810893B2
公开(公告)日:2023-11-07
申请号:US17334937
申请日:2021-05-31
Applicant: International Business Machines Corporation
Inventor: William Emmett Bernier , Bing Dang , John Knickerbocker , Son Kim Tran , Mario J. Interrante
IPC: H01L23/00 , H01L23/552 , H01L23/498 , H01L25/065 , H01L23/367 , H01L23/60
CPC classification number: H01L24/81 , H01L23/367 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/552 , H01L23/60 , H01L24/09 , H01L25/0655 , H01L2224/08238 , H01L2224/16225 , H01L2224/81192 , H01L2924/014 , H01L2924/0105 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/1579 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/15738 , H01L2924/15787 , H01L2924/19105 , H01L2924/1461 , H01L2924/00
Abstract: An interposer sandwich structure includes a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes an attachment for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.
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公开(公告)号:US11710669B2
公开(公告)日:2023-07-25
申请号:US16882624
申请日:2020-05-25
Applicant: International Business Machines Corporation
Inventor: John Knickerbocker , Bing Dang , Qianwen Chen , Joshua M. Rubin , Arvind Kumar
IPC: H01L21/66 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: H01L22/20 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2225/06513 , H01L2225/06541
Abstract: One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.
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15.
公开(公告)号:US20230100769A1
公开(公告)日:2023-03-30
申请号:US17488968
申请日:2021-09-29
Applicant: International Business Machines Corporation
Inventor: John Knickerbocker , Mukta Ghate Farooq , Katsuyuki Sakuma
IPC: H01L23/00 , H01L23/538 , H01L23/66 , H01L21/683 , H01L21/48 , H01P3/00 , H01P11/00 , H01L23/367
Abstract: An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.
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公开(公告)号:US20230098054A1
公开(公告)日:2023-03-30
申请号:US17449280
申请日:2021-09-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Lei Shan , Daniel Joseph Friedman , Griselda Bonilla , John Knickerbocker
IPC: H01L23/538 , H01L23/15 , H01L23/498 , H01L21/48
Abstract: A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.
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公开(公告)号:US11307147B2
公开(公告)日:2022-04-19
申请号:US16796763
申请日:2020-02-20
Applicant: International Business Machines Corporation
Inventor: Minhua Lu , Vince Siu , Russell Budd , Evan Colgan , John Knickerbocker
Abstract: Techniques for colorimetric based test strip analysis and reader system are provided. In one aspect, a method of test strip analysis includes: illuminating a test strip wetted with a sample with select spectrums of light, wherein the test strip includes test pads that are configured to change color in the presence of an analyte in the sample; obtaining at least one digital image of the test strip; and analyzing color intensity from the at least one digital image against calibration curves to determine an analyte concentration in the sample with correction for one or more interference substances in the sample that affect the color intensity. A calibration method and a reader device are also provided.
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公开(公告)号:US11171374B2
公开(公告)日:2021-11-09
申请号:US15841720
申请日:2017-12-14
Applicant: International Business Machines Corporation
Inventor: Qianwen Chen , Bing Dang , John Knickerbocker , Bo Wen
IPC: H01M10/04 , H01M50/116 , H01M10/0525 , H01M10/0565 , H01M10/0562 , H01M6/40 , H01M6/18 , H01M50/10 , H01M50/20 , H01M50/183
Abstract: Systems and/or techniques associated with a solid-state microbattery packaging system are provided. In one example, a device comprises a substrate layer and a tape substrate layer. The substrate layer is associated with a set of solid-state microbattery components. The tape substrate comprises a releasable adhesive material and a polymer sealing material. A conductive surface associated with the set of solid-state microbattery components is disposed on the releasable adhesive material of the tape substrate layer.
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公开(公告)号:US11094407B2
公开(公告)日:2021-08-17
申请号:US16440032
申请日:2019-06-13
Applicant: International Business Machines Corporation
Inventor: John Knickerbocker , Li-Wen Hung , Bing Dang , Katsuyuki Sakuma , Jeffrey Donald Gelorme , Rajeev Narayanan , Qianwen Chen
Abstract: A drug delivery form includes a drug and electronics. The electronics includes memory(ies) having drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The electronics includes communication circuitry configured to read data from and write data to the drug delivery form information. An apparatus includes memory(ies) having computer readable code, and processor(s). The processor(s) cause the apparatus to perform operations including communicating with a drug delivery form including a drug and drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The processor(s) cause the apparatus to perform reading data from or writing data into the drug and drug delivery form information.
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公开(公告)号:US10903153B2
公开(公告)日:2021-01-26
申请号:US16194377
申请日:2018-11-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: John Knickerbocker , Bing Dang , Raymond Horton , Joana Maria
IPC: H01L23/498 , H01L23/48 , H01L21/683 , H01L21/48 , H01L21/20 , H01L21/768
Abstract: Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.
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