公开(公告)号：US20160190071A1

公开(公告)日：2016-06-30

申请号：US14585323

申请日：2014-12-30

Applicant: International Business Machines Corporation

Inventor： Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H01L23/00 ,  B23K20/02

CPC classification number: H01L23/562 ,  B23K1/0016 ,  B23K3/0623 ,  B23K20/023 ,  B23K20/026 ,  H01L24/83 ,  H01L2224/8382

Abstract: A method of bonding components is disclosed. One embodiment of such a method includes applying both heat and pressure to a stack of components that includes an interposer with a reduced degree of warpage. Reducing the distance between the interposer and a first component of the stack of the components until a spacer prevents further reduction of that space. Then, cooling the stack of components while the pressure is maintained such that the degree of warpage of the interposer remains reduced.

Abstract translation: 公开了粘接部件的方法。 这种方法的一个实施例包括将热和压力应用于包括具有降低的翘曲度的插入件的部件堆叠。 减小插入器与组件的堆叠的第一部件之间的距离，直到间隔件阻止该空间的进一步减小。 然后，在保持压力的同时冷却组件堆叠，使得插入件的翘曲程度仍然降低。

公开(公告)号：US20210288022A1

公开(公告)日：2021-09-16

申请号：US17334937

申请日：2021-05-31

Applicant: International Business Machines Corporation

Inventor： William EMMETT BERNIER ,  BING DANG ,  JOHN KNICKERBOCKER ,  SON KIM TRAN ,  Mario J. Interrante

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/498 ,  H01L25/065 ,  H01L23/367 ,  H01L23/60

Abstract: An interposer sandwich structure includes a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes an attachment for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.

公开(公告)号：US10262970B2

公开(公告)日：2019-04-16

申请号：US15215934

申请日：2016-07-21

Applicant: International Business Machines Corporation

Inventor： Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H01L23/00 ,  H01L21/50 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

公开(公告)号：US20160233190A1

公开(公告)日：2016-08-11

申请号：US15131171

申请日：2016-04-18

Applicant: International Business Machines Corporation

Inventor： William E. Bernier ,  Bing Dang ,  Mario J. Interrante ,  John U. Knickerbocker ,  Son K. Tran

IPC: H01L23/00 ,  H01L23/367 ,  H01L25/065 ,  H01L23/60 ,  H01L23/552 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/552 ,  H01L23/60 ,  H01L24/09 ,  H01L25/0655 ,  H01L2224/08238 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15738 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.

Abstract translation: 插入器夹层结构包括顶部插入器和封装集成电路电子器件的底部插入器，其包括用于将器件附接到底部插入器的装置，以及将顶部插入件连接到底部插入器的互连结构。 除了底部插入器之外，顶部插入器还可以直接连接到芯片载体。 该结构提供了在小型化3D封装中防止静电放电（ESD），电磁干扰（EMI）和电磁导电（EMC））的器件的屏蔽和保护。

公开(公告)号：US09224712B2

公开(公告)日：2015-12-29

申请号：US14177348

申请日：2014-02-11

Applicant: International Business Machines Corporation

Inventor： Marcus E. Interrante ,  Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H01L21/30 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  B23K3/06

CPC classification number: H01L24/81 ,  B23K3/0623 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/131 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/75983 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81075 ,  H01L2224/8109 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/2064 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/0665 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2221/68381 ,  H01L2224/83 ,  H01L2924/00

Abstract: An interposer structure containing a first set of solder balls is placed in proximity to a vacuum distribution plate which has a planar contact surface and a plurality of openings located therein. A vacuum is then applied through the openings within the vacuum distribution plate such that the first set of solder balls are suspended within the plurality of openings and the interposer structure conforms to the planar contact surface of the vacuum distribution plate. A semiconductor chip containing a second set of solder balls is tacked to a surface of the interposer structure. A substrate is then brought into contact with a surface of the interposer structure containing the first set of solder balls, and then a solder reflow and underfill processes can be performed. Warping of the interposer structure is substantially eliminated using the vacuum distribution plate mentioned above.

Abstract translation: 包含第一组焊球的插入器结构放置在真空分配板附近，真空分配板具有平面接触表面和位于其中的多个开口。 然后通过真空分配板中的开口施加真空，使得第一组焊球悬挂在多个开口内，并且插入件结构符合真空分配板的平面接触表面。 包含第二组焊球的半导体芯片被固定到中介层结构的表面。 然后将衬底与包含第一组焊球的内插器结构的表面接触，然后可以进行焊料回流和底部填充处理。 使用上述真空分配板基本上消除了内插器结构的翘曲。

公开(公告)号：US20150228614A1

公开(公告)日：2015-08-13

申请号：US14177348

申请日：2014-02-11

Applicant: International Business Machines Corporation

Inventor： MARCUS E INTERRANTE ,  Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H01L23/00 ,  H01L23/498 ,  B23K3/06 ,  H01L25/065 ,  H01L21/683 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L24/81 ,  B23K3/0623 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/131 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/75983 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81075 ,  H01L2224/8109 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/2064 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/0665 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2221/68381 ,  H01L2224/83 ,  H01L2924/00

Abstract: An interposer structure containing a first set of solder balls is placed in proximity to a vacuum distribution plate which has a planar contact surface and a plurality of openings located therein. A vacuum is then applied through the openings within the vacuum distribution plate such that the first set of solder balls are suspended within the plurality of openings and the interposer structure conforms to the planar contact surface of the vacuum distribution plate. A semiconductor chip containing a second set of solder balls is tacked to a surface of the interposer structure. A substrate is then brought into contact with a surface of the interposer structure containing the first set of solder balls, and then a solder reflow and underfill processes can be performed. Warping of the interposer structure is substantially eliminated using the vacuum distribution plate mentioned above.

Abstract translation: 包含第一组焊球的插入器结构放置在真空分配板附近，真空分配板具有平面接触表面和位于其中的多个开口。 然后通过真空分配板中的开口施加真空，使得第一组焊球悬挂在多个开口内，并且插入件结构符合真空分配板的平面接触表面。 包含第二组焊球的半导体芯片被固定到中介层结构的表面。 然后将衬底与包含第一组焊球的内插器结构的表面接触，然后可以进行焊料回流和底部填充处理。 使用上述真空分配板基本上消除了内插器结构的翘曲。

公开(公告)号：US20140209666A1

公开(公告)日：2014-07-31

申请号：US13753025

申请日：2013-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75502 ,  H01L2224/75743 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/81024 ,  H01L2224/81121 ,  H01L2224/81204 ,  H01L2224/81211 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/8191 ,  H01L2224/81948 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method for packaging a semiconductor device includes attaching a first array of solder material to a first surface of an interposer; bringing the first array of solder material into physical contact with a laminate; and initially bonding the interposer to the laminate by applying a first temperature and pressure gradient to the first array of solder material such that a melting temperature of the first array of solder material is not exceeded.

Abstract translation: 一种用于封装半导体器件的方法包括将第一焊料材料阵列附着到中介层的第一表面; 将第一阵列焊料材料与层压体物理接触; 并且首先通过向第一焊料材料阵列施加第一温度和压力梯度来将所述插入件接合到所述层压体，使得焊料材料的第一阵列的熔化温度不被超过。

公开(公告)号：US20180084649A1

公开(公告)日：2018-03-22

申请号：US15814697

申请日：2017-11-16

Applicant: International Business Machines Corporation

Inventor： Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H05K3/34 ,  H05K1/18 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H05K1/02 ,  H01L21/50 ,  H01L21/48

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/50 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/17 ,  H01L24/75 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/75252 ,  H01L2224/75272 ,  H01L2224/75283 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/0271 ,  H05K1/181 ,  H05K3/3494 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/1316 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

公开(公告)号：US09860996B2

公开(公告)日：2018-01-02

申请号：US15214535

申请日：2016-07-20

Applicant: International Business Machines Corporation

Inventor： Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H05K3/34 ,  H01L21/50 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K3/3494 ,  H01L21/4853 ,  H01L21/50 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/75252 ,  H01L2224/75272 ,  H01L2224/75283 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/0271 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/1316 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

公开(公告)号：US20160330848A1

公开(公告)日：2016-11-10

申请号：US15215934

申请日：2016-07-21

Applicant: International Business Machines Corporation

Inventor： Mario J. Interrante ,  Katsuyuki Sakuma

IPC: H05K3/34 ,  H05K1/02 ,  H01L21/56 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/50 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/17 ,  H01L24/75 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/75252 ,  H01L2224/75272 ,  H01L2224/75283 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/0271 ,  H05K1/181 ,  H05K3/3494 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/1316 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.