公开(公告)号：US10930779B2

公开(公告)日：2021-02-23

申请号：US16670101

申请日：2019-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.

公开(公告)号：US20200343257A1

公开(公告)日：2020-10-29

申请号：US16391982

申请日：2019-04-23

Applicant: International Business Machines Corporation

Inventor： Jeng-Bang Yau ,  Alexander Reznicek ,  Bahman Hekmatshoartabari ,  Karthik Balakrishnan

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/786 ,  G01T1/02

Abstract: The dosimeter has two vertical field effect transistors (VFETs), each VFET with a bottom and top source/drain and channel between them. An implanted charge storage region material lies between and in contact with each of the vertical channels. A trapped charge is within the implanted charge storage region. The amount of the trapped charge is related to an amount of radiation that passes through the implanted charge storage region.

公开(公告)号：US20200212226A1

公开(公告)日：2020-07-02

申请号：US16238263

申请日：2019-01-02

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Kangguo Cheng ,  Karthik Balakrishnan ,  Pouya Hashemi

IPC: H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/423 ,  H03K19/0948

Abstract: An inverter that includes an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET) vertically stacked one atop the other and containing a buried metal semiconductor alloy strap that connects a drain region of the nFET to a drain region of the pFET is provided. Also, provided is a cross-coupled inverter pair with nFETs and pFETs stacked vertically.

公开(公告)号：US10692859B2

公开(公告)日：2020-06-23

申请号：US15619918

申请日：2017-06-12

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L27/06 ,  H01L29/861 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.

公开(公告)号：US10658507B2

公开(公告)日：2020-05-19

申请号：US16450367

申请日：2019-06-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.

公开(公告)号：US20200152624A1

公开(公告)日：2020-05-14

申请号：US16739853

申请日：2020-01-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/07 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  G11C7/06

Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.

公开(公告)号：US10636804B1

公开(公告)日：2020-04-28

申请号：US16192140

申请日：2018-11-15

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

IPC: H01L27/11551 ,  H01L27/11521 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/11517 ,  H01L27/11568 ,  H01L27/092 ,  H01L27/112 ,  H01L21/84 ,  H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L29/788 ,  G11C16/02

Abstract: A stacked FinFET programmable inverter is provided that includes a pFET gate structure including a floating gate and a thicker gate dielectric material layer than a gate dielectric material layer of an nFET gate structure stacked either above, or below, the nFET gate structure. In one embodiment, the pFET gate structure is below the nFET gate structure. In another embodiment, the pFET gate structure is above the nFET gate structure. The pFET gate structure contacts a sidewall of one semiconductor fin portion of a fin stack, while the nFET gate structure contacts a sidewall of another of the semiconductor fin portion of the same fin stack; the two semiconductor fin portions are separated by an insulator fin portion.

公开(公告)号：US10600878B2

公开(公告)日：2020-03-24

申请号：US16370025

申请日：2019-03-29

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/283 ,  H01L29/165 ,  H01L29/423

Abstract: A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.

公开(公告)号：US20200066874A1

公开(公告)日：2020-02-27

申请号：US16671844

申请日：2019-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Jeng-Bang Yau ,  Alexander Reznicek ,  Tak H. Ning

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L27/11521

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

公开(公告)号：US10522678B2

公开(公告)日：2019-12-31

申请号：US15834593

申请日：2017-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.