公开(公告)号：US11119781B2

公开(公告)日：2021-09-14

申请号：US16216659

申请日：2018-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  Sanjeev Ghai

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/30 ,  G06F9/52 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0888 ,  G06F12/0831

Abstract: A data processing system includes multiple processing units all having access to a shared memory. A processing unit of the data processing system includes a processor core including an upper level cache, core reservation logic that records addresses in the shared memory for which the processor core has obtained reservations, and an execution unit that executes memory access instructions including a fronting load instruction. Execution of the fronting load instruction generates a load request that specifies a load target address. The processing unit further includes lower level cache that, responsive to receipt of the load request and based on the load request indicating an address match for the load target address in the core reservation logic, protects the load target address against access by any conflicting memory access request during a protection interval following servicing of the load request.

公开(公告)号：US10831607B2

公开(公告)日：2020-11-10

申请号：US16049721

申请日：2018-07-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  Sanjeev Ghai ,  Hung Doan

IPC: G06F11/00 ,  G06F11/14 ,  G06F12/0802 ,  G06F9/30 ,  G06F30/30

Abstract: In a processing unit, a processor core executes instructions in a plurality of simultaneous hardware threads, where multiple of the plurality of hardware threads concurrently execute memory transactions. A transactional memory circuit in the processing unit tracks transaction footprints of the memory transactions of the multiple hardware thread. In response to detecting failure of a given memory transaction of one of the plurality of multiple threads due to an overflow condition, the transactional memory circuit transitions to a throttled operating mode and reduces a number of hardware threads permitted to concurrently execute memory transactions.

公开(公告)号：US10152322B2

公开(公告)日：2018-12-11

申请号：US15243413

申请日：2016-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bradly G. Frey ,  Sanjeev Ghai ,  Guy L. Guthrie ,  Cathy May ,  William J. Starke ,  Derek E. Williams

IPC: G06F9/30 ,  G06F12/0811 ,  G06F12/0879 ,  G06F12/1081 ,  G06F13/28 ,  G06F12/0831

Abstract: A processor core has a store-through upper level cache and a store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instruction and a plurality of paste-type instructions, the processor core transmits a corresponding plurality of copy-type and paste-type requests to the lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the lower level cache copies a respective one of a plurality of data granules from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer. In response to receipt of each paste-type request, the lower level cache writes a respective one of the plurality of data granules from the non-architected buffer to a respective storage location specified by the destination real address of that paste-type request.

公开(公告)号：US09471491B2

公开(公告)日：2016-10-18

申请号：US14073553

申请日：2013-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F11/14

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016

Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.

Abstract translation: 用于操作高可用性（HA）数据处理系统的技术包括响应于在高速缓存处接收到HA注销指示，启动高速缓存的散步以定位包括HA数据的高速缓存中的高速缓存行。 响应于确定高速缓存行包括HA数据，高速缓存行的地址被记录在高速缓存中的缓冲器的第一部分中。 响应于缓冲器的第一部分达到确定的填充级别，缓冲器的第一部分的内容被记录到另一个存储器。 响应缓存中的所有缓存行被行走，高速缓存行走终止。

公开(公告)号：US20150052312A1

公开(公告)日：2015-02-19

申请号：US14038026

申请日：2013-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Jonathan R. Jackson ,  Derek E. Williams

IPC: G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0864 ,  G06F12/123

Abstract: A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.

Abstract translation: 处理单元包括处理器核和高速缓冲存储器。 高速缓冲存储器中的条目被分组在多个同余类中。 高速缓冲存储器包括跟踪逻辑，其跟踪事务占用，包括由存储器事务的事务存储器访问请求访问的高速缓存行。 高速缓冲存储器响应于接收指定具有映射到同余类的目标地址的目标高速缓存行的存储器访问请求，形成包含事务占用空间内的高速缓存行的一致性类中的一组工作方式，并更新 一致类中缓存行的替换顺序。 基于工作集中的至少一个高速缓存行的成员身份，该更新将至少一个不是目标高速缓存行的高速缓存行促进到其中至少一个高速缓存行不太可能被替换的替换顺序位置。

公开(公告)号：US10725937B2

公开(公告)日：2020-07-28

申请号：US16049011

申请日：2018-07-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  Sanjeev Ghai

IPC: G06F12/14 ,  G06F12/084

Abstract: A data processing system includes multiple processing units all having access to a shared memory. A processing unit includes a processor core that executes memory access instructions including a store-conditional instruction that generates a store-conditional request specifying a store target address and store data. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The processing unit additional includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request during a protection window extension following servicing of the store-conditional request.

公开(公告)号：US10140052B2

公开(公告)日：2018-11-27

申请号：US15243385

申请日：2016-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Sanjeev Ghai ,  William J. Starke

IPC: G06F3/06 ,  G06F12/0897 ,  G06F12/10 ,  G06F13/40

Abstract: A data processing system includes a processor core having a store-through upper level cache and a store-in lower level cache. In response to a first instruction, the processor core generates a copy-type request and transmits the copy-type request to the lower level cache, where the copy-type request specifies a source real address. In response to a second instruction, the processor core generates a paste-type request and transmits the paste-type request to the lower level cache, where the paste-type request specifies a destination real address. In response to receipt of the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer, and in response to receipt of the paste-type request, the lower level cache writes the data granule from the non-architected buffer to a storage location specified by the destination real address.

公开(公告)号：US09430382B2

公开(公告)日：2016-08-30

申请号：US14170106

申请日：2014-01-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/0811 ,  G06F12/08 ,  G06F12/12 ,  G06F11/14

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016

Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.

Abstract translation: 用于操作高可用性（HA）数据处理系统的技术包括响应于在高速缓存处接收到HA注销指示，启动高速缓存的散步以定位包括HA数据的高速缓存中的高速缓存行。 响应于确定高速缓存行包括HA数据，高速缓存行的地址被记录在高速缓存中的缓冲器的第一部分中。 响应于缓冲器的第一部分达到确定的填充级别，缓冲器的第一部分的内容被记录到另一个存储器。 响应缓存中的所有缓存行被行走，高速缓存行走终止。

公开(公告)号：US09304936B2

公开(公告)日：2016-04-05

申请号：US14100356

申请日：2013-12-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Hugh Shen ,  Derek E. Williams

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F13/00 ,  G06F13/28 ,  G06F9/38

CPC classification number: G06F12/0888 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3836 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0833 ,  G06F12/0895 ,  G06F12/128

Abstract: In response to receipt of a store-conditional (STCX) request of a processor core, the STCX request is buffered in an entry of a store queue for eventual service by a read-claim (RC) machine by reference to a cache array, and the STCX request is concurrently transmitted via a bypass path bypassing the store queue. In response to dispatch logic dispatching the STCX request transmitted via the bypass path to the RC machine for service by reference to the cache array, the entry of the STCX request in the store queue is updated to prohibit selection of the STCX request in the store queue for service. In response to the STCX request transmitted via the bypass path not being dispatched by the dispatch logic, the STCX is thereafter transmitted from the store queue to the dispatch logic and dispatched to the RC machine for service by reference to the cache array.

公开(公告)号：US20150052311A1

公开(公告)日：2015-02-19

申请号：US14037923

申请日：2013-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Jonathan R. Jackson ,  Derek E. Williams

IPC: G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0828

Abstract: In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.

Abstract translation: 在具有处理器核心和包括支持处理器核心的高速缓冲存储器的共享存储器系统的数据处理系统中，处理器核心响应于执行正在执行的存储器事务中的存储器访问指令执行事务存储器访问请求 由处理器核心。 响应于接收事务存储器访问请求，缓存存储器的调度逻辑评估用于调度的事务存储器访问请求，其中评估包括确定存储器事务是否具有故障事务状态。 响应于确定存储器事务具有失败的事务状态，分派逻辑不会缓存高速缓冲存储器的服务存储器访问请求，并且至少响应于事务存储器访问请求更新缓存存储器的替换顺序信息 。