公开(公告)号：US20210111066A1

公开(公告)日：2021-04-15

申请号：US16598058

申请日：2019-10-10

Applicant: International Business Machines Corporation

Inventor： Somnath Ghosh ,  Hsueh-Chung Chen ,  Yongan Xu ,  Yann Mignot ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311

Abstract: A method includes applying a first metallic layer having a first metallic material onto a substrate of a semiconductor component. The method further includes removing portions of the first metallic layer to form a first metallic line. The method further includes creating an opening in the first metallic line. The method also includes depositing a dielectric material on the substrate. The method further includes forming at least one trench in the dielectric material. The method also includes depositing a second metallic material within the at least one trench to form a second metallic line. At least the first and second metallic lines and the dielectric material form an interconnect structure of the semiconductor component.

公开(公告)号：US10957552B2

公开(公告)日：2021-03-23

申请号：US16666948

申请日：2019-10-29

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Ekmini Anuja De Silva ,  Su Chen Fan ,  Yann Mignot

IPC: H01L21/308 ,  G03F1/22 ,  H01L21/033

Abstract: Semiconductor structures fabricated via extreme ultraviolet (EUV) lithographic patterning techniques implementing directional deposition on a EUV resist mask improves selectivity and critical dimension control during the patterning of features in multiple layers of the semiconductor substrate. A semiconductor structure includes a substrate structure having an extreme ultraviolet resist mask disposed over one or more additional layers of the substrate structure. The extreme ultraviolet resist mask defines patterning features. A hard mask layer including a hard mask material is disposed on the extreme ultraviolet resist mask and covers the patterning features of the extreme ultraviolet resist mask.

公开(公告)号：US20210082747A1

公开(公告)日：2021-03-18

申请号：US16572045

申请日：2019-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Hsueh-Chung Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

Abstract: A method of forming vias and skip vias is provided. The method includes forming a blocking layer on an underlying layer, and forming an overlying layer on the blocking layer. The method further includes opening a hole in the overlying layer that overlaps the blocking layer, and etching past the blocking layer into the underlying layer to form a second hole that is smaller than the hole in the overlying layer.

公开(公告)号：US10923401B2

公开(公告)日：2021-02-16

申请号：US16172205

申请日：2018-10-26

Applicant: International Business Machines Corporation

Inventor： Andrew Greene ,  Marc Bergendahl ,  Ekmini A. De Silva ,  Alex Joseph Varghese ,  Yann Mignot ,  Matthew T. Shoudy ,  Gangadhara Raja Muthinti ,  Dallas Lea

IPC: H01L21/8234 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/3213

Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.

公开(公告)号：US10886197B2

公开(公告)日：2021-01-05

申请号：US16798374

申请日：2020-02-23

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Muthumanickam Sankarapandian ,  Yongan Xu

IPC: H01L23/48 ,  H01L21/768

Abstract: An Nblock layer is deposited onto a semiconductor substrate that includes metal deposits. A titanium nitride (TiN) layer is deposited directly onto the Nblock layer; an oxide layer is deposited directly onto the TiN layer; and a via hole is formed through the oxide and TiN layer to contact bottom interconnect. The via hole is aligned to one of the metal deposits in the substrate.

公开(公告)号：US20200381354A1

公开(公告)日：2020-12-03

申请号：US16425524

申请日：2019-05-29

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Hosadurga Shobha ,  Hsueh-Chung Chen ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Techniques for fabricating a metallic interconnect include forming a first metallization layer that includes a first dielectric layer, a first metallic layer formed in the first dielectric layer and a first capping layer formed on the first dielectric layer and the first metallic layer and forming a second metallization layer that includes a second dielectric layer, a second metallic layer formed in the second dielectric layer and a second capping layer formed on the second dielectric layer and the second metallic layer. A channel is etched in the second capping layer, second dielectric layer, and first capping layer that exposes a portion of the first metallic layer and a portion of the second metallic layer. A metallic interconnect structure is formed in the channel in contact with the exposed portion of the first metallic layer and the exposed portion of the second metallic layer.

公开(公告)号：US10679892B1

公开(公告)日：2020-06-09

申请号：US16288940

申请日：2019-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Chih-Chao Yang ,  Hosadurga Shobha

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/311

Abstract: A method is presented for reducing a resistance-capacitance product and RIE lag in a semiconductor device. The method includes depositing a first ultra-low-k (ULK) material over a dielectric cap, the first ULK material defining a recess, filling the recess with a second ULK material, the second ULK material being different than the first ULK material, where the first and second ULK materials are formed in a common metal level of a back-end-of-the-line (BEOL) structure, forming first trenches within the first ULK material and second trenches within the second ULK material, and filling the first and second trenches with a conductive material.

公开(公告)号：US10658190B2

公开(公告)日：2020-05-19

申请号：US16139819

申请日：2018-09-24

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Ekmini Anuja De Silva ,  Su Chen Fan ,  Yann Mignot

IPC: H01L21/308 ,  G03F1/22 ,  H01L21/033

Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement directional deposition on the EUV resist mask to improve selectivity and critical dimension control during the patterning of features in multiple layers. A hard mask material is deposited on a substrate structure using directional deposition. The hard mask material forms a hard mask layer that covers patterning features of an EUV resist mask of the substrate structure. The hard mask material is etched selective to a layer underlying the EUV resist mask to remove portions of the hard mask material that were deposited on the underlying layer during the directional deposition without uncovering the patterning features of the EUV resist mask. At least one layer of the substrate structure is patterned based on the EUV resist mask and the hard mask layer.

公开(公告)号：US20200066525A1

公开(公告)日：2020-02-27

申请号：US16669835

申请日：2019-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Lawrence A. Clevenger ,  Yann Mignot ,  Cornelius Brown Peethala

IPC: H01L21/033 ,  G03F7/00 ,  H01L21/027 ,  G03F7/20 ,  G03F7/09 ,  H01L21/02 ,  H01L21/3105 ,  G03F7/16

Abstract: A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a memorization layer over a plurality of mandrels and a plurality of non-mandrels, and applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern.

公开(公告)号：US20200058585A1

公开(公告)日：2020-02-20

申请号：US16104403

申请日：2018-08-17

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Junli Wang ,  Yann Mignot ,  Joe Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3105

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.