公开(公告)号：US20210028175A1

公开(公告)日：2021-01-28

申请号：US17037972

申请日：2020-09-30

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Zheng Xu ,  Dexin Kong ,  Kangguo Cheng

IPC: H01L27/105 ,  H01L21/8229 ,  H01L29/06

Abstract: A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.

公开(公告)号：US20200273756A1

公开(公告)日：2020-08-27

申请号：US16284261

申请日：2019-02-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Dexin Kong ,  Zhenxing Bi

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes a substrate with a first semiconductor fin and a second semiconductor fin formed thereon. A pair of opposing dielectric trench spacers are between the first and second semiconductor fins. The opposing dielectric trench spacers define an isolation region therebetween. The semiconductor device further includes a shallow trench isolation (STI) element formed in the isolation region. The STI element includes a lower portion on the substrate and an upper portion located opposite the lower portion. The upper portion extends above an upper end of the dielectric trench spacers.

公开(公告)号：US10741456B2

公开(公告)日：2020-08-11

申请号：US16156391

申请日：2018-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Zhenxing Bi

IPC: H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

Abstract: Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.

公开(公告)号：US20200235204A1

公开(公告)日：2020-07-23

申请号：US16250585

申请日：2019-01-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Zhenxing Bi ,  Dexin Kong

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

Abstract: A semiconductor structure is provided that includes active semiconductor fins that have a uniform fin channel height. The uniform fin channel height is achieved by forming semiconductor fins (active and sacrificial) on an entirety of semiconductor substrate thus there is no loading effect during a subsequently performed dielectric etch step which can lead to fin channel height variation and ultimately variation in device characteristics. A trench isolation structure is located adjacent to the active semiconductor fins. The trench isolation structure includes at least one dielectric plug having a second width and a dielectric pillar having a first width located on each side of the at least one dielectric plug. The second width of the at least one dielectric plug is less than the first width of each dielectric pillar, yet equal to a width of each semiconductor fin.

公开(公告)号：US10714569B1

公开(公告)日：2020-07-14

申请号：US16366671

申请日：2019-03-27

Applicant: International Business Machines Corporation

Inventor： Dexin Kong ,  Kangguo Cheng ,  Juntao Li ,  Zhenxing Bi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: Strained nanosheet field effect transistors (FETs) using a phase change material are described herein. In some embodiments, a semiconductor device can comprise alternating layers of a channel material and a phase change material to produce strained nanosheet field effect transistors, wherein the layers of the phase change material cause a strain in the layers of the channel material. The phase change material comprises germanium antimony telluride. The germanium antimony telluride crystallizes into a crystalline germanium antimony telluride based on annealing above 300 degrees Celsius and a volume of the crystalline germanium antimony telluride is reduced up to six percent relative to an initial volume the germanium antimony telluride to cause the strain in the layers of the channel material. The semiconductor device can also comprise source and drain epitaxial growths on both ends of the layers of the channel material that lock the strain in the layers of the channel material.

公开(公告)号：US20200144118A1

公开(公告)日：2020-05-07

申请号：US16181914

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Zhenxing Bi ,  Dexin Kong

IPC: H01L21/768 ,  H01L23/522

Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

公开(公告)号：US20200126805A1

公开(公告)日：2020-04-23

申请号：US16165786

申请日：2018-10-19

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Muthumanickam Sankarapandian ,  Richard A. Conti ,  Michael P. Belyansky

IPC: H01L21/311 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: Highly selective dry etching techniques for VFET STI recess are provided. In one aspect, a method for dry etching includes: contacting a wafer including an oxide with at least one etch gas under conditions sufficient to etch the oxide at a rate of less than about 30 Å/min; removing a byproduct of the etch from the wafer using a thermal treatment; and repeating the contacting step followed by the removing step multiple times until a desired recess of the oxide has been achieved. A method of forming a VFET device is also provided.

公开(公告)号：US10586856B2

公开(公告)日：2020-03-10

申请号：US16009196

申请日：2018-06-14

Applicant: International Business Machines Corporation

Inventor： Nicolas Loubet ,  Julien Frougier ,  Wenyu Xu ,  Zhenxing Bi

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/775

Abstract: A semiconductor device is described. The semiconductor device includes a nanosheet stack including a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet. The semiconductor device includes a gate formed in a direction orthogonal to the plane of the nanosheet stack, with a gate spacer positioned along a sidewall of the gate. The semiconductor device includes an inner spacer liner deposited around the nanosheet stack and the gate spacer. A first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet. A second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet.

公开(公告)号：US20200051806A1

公开(公告)日：2020-02-13

申请号：US16659691

申请日：2019-10-22

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate.

公开(公告)号：US20190393344A1

公开(公告)日：2019-12-26

申请号：US16291367

申请日：2019-03-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Peng Xu ,  Heng Wu ,  Zhenxing Bi

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417

Abstract: An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.