公开(公告)号：US09450613B2

公开(公告)日：2016-09-20

申请号：US14327796

申请日：2014-07-10

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Ulrich Backhausen ,  Thomas Rabenalt ,  Michael Goessel ,  Klaus Oberlaender ,  Christian Badack

IPC: H03M13/00 ,  H03M13/15

CPC classification number: H03M13/151 ,  H03M13/152 ,  H03M13/155 ,  H03M13/1575 ,  H03M13/159 ,  H03M13/616 ,  H03M13/6575

Abstract: A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.

Abstract translation: 一种电路，包括：校正子发生器，被配置为基于奇偶校验矩阵产生校正子，并且提供包括第一组位和第二组位的二进制字。 对于第一组位，奇偶校验矩阵提供第一组内的可校正位错误的纠错，对于第二组位，第二组中的可检测位错误的错误检测由奇偶校验矩阵 。

公开(公告)号：US20150039952A1

公开(公告)日：2015-02-05

申请号：US14447806

申请日：2014-07-31

Applicant: Infineon Technologies AG

Inventor： Michael Goessel ,  Sven Hosp ,  Guenther Niess ,  Klaus Oberlaender

IPC: G11C29/10 ,  G06F11/263

CPC classification number: G11C29/10 ,  G06F11/1048 ,  G06F11/263 ,  G11C29/42 ,  G11C2029/0411

Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C). Furthermore, the error detection circuit (12) is designed, for the case where the control signal present assumes a second value, which is different from the first value, and the code word that is inverted in the subset (M) of bits was written to the memory location, to determine on the basis of the data word read out from the memory (11) whether a memory error is present if the code word that is inverted in the subset (M) of bits is not a code word of the error detection code (C).

Abstract translation: 提供了一种用于检测存储器错误的电路装置。 电路装置包括存储器（11）和错误检测电路（12）。 电路装置被设计成存储错误检测码（C）的代码字或在存储器（11）中在存储器（11）的位的子集（M））中反转的代码字，并读出数据字 从存储器（11）从存储器位置。 如果数据字不是错误检测码（C）的代码字，则对于存在的控制信号呈现第一值的情况，错误检测电路（12）被设计为指示存储器错误。 此外，对于存在的控制信号呈现与第一值不同的第二值，并且在位的子集（M）中被反转的代码字被写入的情况下，设计错误检测电路（12） 到存储器位置，基于从存储器（11）读出的数据字来确定是否存在存储器错误，如果在位的子集（M）中被反转的代码字不是存储器的代码字 错误检测码（C）。