公开(公告)号：US10957686B2

公开(公告)日：2021-03-23

申请号：US16744693

申请日：2020-01-16

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40 ,  H01L49/02 ,  H01L29/739 ,  H01L29/808

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor. A method of producing the semiconductor device is also described.

公开(公告)号：US10593799B2

公开(公告)日：2020-03-17

申请号：US16100496

申请日：2018-08-10

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Karl-Heinz Bach ,  Peter Brandl ,  Andrew Christopher Graeme Wood

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/225 ,  H01L21/266 ,  H01L29/40 ,  H01L21/265

Abstract: A semiconductor component includes a field-effect transistor arrangement having a drift zone and body region between the drift zone and a first surface of a semiconductor body. Trench structures of a first type extend from the first surface into the semiconductor body and have a maximum lateral dimension at the first surface which is less than a depth of first and second ones of the trench structures. A net doping concentration at a reference depth at a first location in the drift zone is at least 10% greater than at a second location in the drift zone at the reference depth, which is located between the body region and a bottom of the first trench structure. The first location is at the same first lateral distance from the first and second trench structures. The second location is at the same second lateral distance from the first and second trench structures.

公开(公告)号：US10186508B2

公开(公告)日：2019-01-22

申请号：US15792492

申请日：2017-10-24

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78 ,  H01L49/02 ,  H01L29/739 ,  H01L29/808 ,  H01L29/40

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20160268422A1

公开(公告)日：2016-09-15

申请号：US15157645

申请日：2016-05-18

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Peter Brandl

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7815

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a continuous first area and a second area, introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer, and forming trenches in the second semiconductor layer in the continuous first area.

Abstract translation: 一种制造半导体器件的方法包括在具有连续的第一区域和第二区域的第一导电类型的半导体衬底上形成第一半导体层，在第一半导体层的连续的第一区域中引入第一导电类型的掺杂剂， 在所述第一半导体层上形成第二半导体层，以及在所述连续的第一区域中在所述第二半导体层中形成沟槽。

公开(公告)号：US09412827B2

公开(公告)日：2016-08-09

申请号：US14879851

申请日：2015-10-09

Applicant: Infineon Technologies AG

Inventor： Peter Brandl ,  Matthias Herman Peri

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/31 ,  H01L21/324 ,  H01L27/088 ,  H01L29/739 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31 ,  H01L21/324 ,  H01L27/088 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A vertical semiconductor device includes a semiconductor body having a backside and extending, in a peripheral area and in a vertical direction substantially perpendicular to the backside, from the backside to a first surface of the semiconductor body, the body including in an active area spaced apart semiconductor mesas extending, in the vertical direction, from the first surface to a main surface arranged above the first surface, in a vertical cross-section the peripheral area extending between the active area and an edge that extends between the back-side and the first surface, in the vertical cross-section each of the mesas including first and second side walls, a first pn-junction extending between the first and second side walls, and a conductive region in Ohmic contact with the mesa and extending from the main surface into the mesa. Gate electrodes are arranged between adjacent mesas and extend across the first pn-junctions.

Abstract translation: 垂直半导体器件包括半导体本体，该半导体本体具有背面，并且在半导体本体的背面至第一表面的周边区域和与背面大致垂直的垂直方向上延伸，该主体包括在间隔开的有源区域中 半导体台面在垂直方向上从第一表面延伸到布置在第一表面上方的主表面，在垂直横截面中，在有效区域和在后侧和第一表面之间延伸的边缘之间延伸的外围区域 在垂直横截面中，每个台面包括第一和第二侧壁，在第一和第二侧壁之间延伸的第一pn结，以及与台面欧姆接触并从主表面延伸的导电区域 台面 栅电极被布置在相邻的台面之间并延伸穿过第一pn结。

公开(公告)号：US20160035845A1

公开(公告)日：2016-02-04

申请号：US14879851

申请日：2015-10-09

Applicant: Infineon Technologies AG

Inventor： Peter Brandl ,  Matthias Herman Peri

IPC: H01L29/423 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31 ,  H01L21/324 ,  H01L27/088 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: A vertical semiconductor device includes a semiconductor body having a backside and extending, in a peripheral area and in a vertical direction substantially perpendicular to the backside, from the backside to a first surface of the semiconductor body, the body including in an active area spaced apart semiconductor mesas extending, in the vertical direction, from the first surface to a main surface arranged above the first surface, in a vertical cross-section the peripheral area extending between the active area and an edge that extends between the back-side and the first surface, in the vertical cross-section each of the mesas including first and second side walls, a first pn-junction extending between the first and second side walls, and a conductive region in Ohmic contact with the mesa and extending from the main surface into the mesa. Gate electrodes are arranged between adjacent mesas and extend across the first pn-junctions.

Abstract translation: 垂直半导体器件包括半导体本体，该半导体本体具有背面，并且在半导体本体的背面至第一表面的周边区域和与背面大致垂直的垂直方向上延伸，该主体包括在间隔开的有源区域中 半导体台面在垂直方向上从第一表面延伸到布置在第一表面上方的主表面，在垂直横截面中，在有效区域和在后侧和第一表面之间延伸的边缘之间延伸的外围区域 在垂直横截面中，每个台面包括第一和第二侧壁，在第一和第二侧壁之间延伸的第一pn结，以及与台面欧姆接触并从主表面延伸的导电区域 台面 栅电极被布置在相邻的台面之间并延伸穿过第一pn结。

公开(公告)号：US09184281B2

公开(公告)日：2015-11-10

申请号：US14067065

申请日：2013-10-30

Applicant: Infineon Technologies AG

Inventor： Peter Brandl ,  Matthias Hermann Peri

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/31 ,  H01L21/324 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/4236 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31 ,  H01L21/324 ,  H01L27/088 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: Producing a vertical semiconductor device includes: providing a semiconductor wafer including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type forming a first pn-junction with the first layer, and a third semiconductor layer of the first conductivity type forming a second pn-junction with the second layer and extending to a main surface of the wafer; forming a hard mask on the main surface that includes hard mask portions spaced apart from each other by first openings; using the hard mask to etch deep trenches from the main surface into the first layer so that mesa regions covered at the main surface by respective hard mask portions are formed between adjacent trenches; filling the trenches and first openings of the hard mask; and etching the hard mask to form second openings in the hard mask at the main surface of the mesas.

Abstract translation: 制造垂直半导体器件包括：提供包括第一导电类型的第一半导体层，与第一层形成第一pn结的第二导电类型的第二半导体层和第一半导体层的第三半导体层的半导体晶片 导电类型与第二层形成第二pn结并延伸到晶片的主表面; 在主表面上形成硬掩模，其包括通过第一开口彼此间隔开的硬掩模部分; 使用硬掩模将深沟槽从主表面蚀刻到第一层中，使得通过相应的硬掩模部分在主表面处覆盖的台面区域形成在相邻的沟槽之间; 填充硬掩模的沟槽和第一开口; 并且蚀刻硬掩模以在台面的主表面处在硬掩模中形成第二开口。