Abstract:
A circuit includes a first power transistor stage internally configured to function as a voltage-controlled current source, a second power transistor stage having an input impedance which varies as a function of input power and an interstage matching network coupling an output of the first power transistor stage to an input of the second power transistor stage. The interstage matching network is configured to provide impedance inversion between the input of the second power transistor stage and the output of the first power transistor stage. The impedance inversion provided by the interstage matching network transforms the first power transistor stage from functioning as a voltage-controlled current source to functioning as a voltage-controlled voltage source at the input of the second power transistor stage.
Abstract:
Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.
Abstract:
An RF transmitter arrangement using analog pre-distortion is disclosed. The arrangement includes lower bandwidth circuitry, an analog pre-distorter, and a non-linear amplifier chain. The lower bandwidth circuitry is configured to generate an analog signal. The analog pre-distorter is configured to apply a non-linear distortion to the analog original signal based on a coupled feedback signal in order to generate an RF output signal. The non-linear amplifier chain is configured to amplify the RF output signal to generate a transmission signal relative to the analog original signal. The coupled feedback signal is derived from the transmission signal.
Abstract:
A non-linear pre-distortion engine maintaining constant peak power at its output is disclosed. The engine includes a compression estimator, a crest factor reduction processor, a digital pre-distorter and a power amplifier. The compression estimator is configured to generate a compression estimate based on an input signal and a feedback signal. The feedback signal is based on an RF output signal. The crest factor reduction processor is configured to reduce a crest factor of the input signal to generate a crest factor reduced signal based on the compression estimate. The digital pre-distorter is configured to apply a pre-distortion to the crest factor reduced signal after an initial phase and generate a pre-distorted signal based on pre-distortion parameters. The power amplifier is configured to amplify the pre-distorted signal to generate the RF output signal. The operation of the chain consisting of pre-distorter and power amplifier is substantially linear and the pre-distorter maintains constant peak power at its output, which eliminates unwanted avalanche or pre-distorter blow-up issues.
Abstract:
A non-linear pre-distortion engine maintaining constant peak power at its output is disclosed. The engine includes a compression estimator, a crest factor reduction processor, a digital pre-distorter and a power amplifier. The compression estimator is configured to generate a compression estimate based on an input signal and a feedback signal. The feedback signal is based on an RF output signal. The crest factor reduction processor is configured to reduce a crest factor of the input signal to generate a crest factor reduced signal based on the compression estimate. The digital pre-distorter is configured to apply a pre-distortion to the crest factor reduced signal after an initial phase and generate a pre-distorted signal based on pre-distortion parameters. The power amplifier is configured to amplify the pre-distorted signal to generate the RF output signal. The operation of the chain consisting of pre-distorter and power amplifier is substantially linear and the pre-distorter maintains constant peak power at its output, which eliminates unwanted avalanche or pre-distorter blow-up issues.
Abstract:
A non-linear pre-distortion engine maintaining constant peak power at its output is disclosed. The engine includes a compression estimator, a crest factor reduction processor, a digital pre-distorter and a power amplifier. The compression estimator is configured to generate a compression estimate based on an input signal and a feedback signal. The feedback signal is based on an RF output signal. The crest factor reduction processor is configured to reduce a crest factor of the input signal to generate a crest factor reduced signal based on the compression estimate. The digital pre-distorter is configured to apply a pre-distortion to the crest factor reduced signal after an initial phase and generate a pre-distorted signal based on pre-distortion parameters. The power amplifier is configured to amplify the pre-distorted signal to generate the RF output signal. The operation of the chain consisting of pre-distorter and power amplifier is substantially linear and the pre-distorter maintains constant peak power at its output, which eliminates unwanted avalanche or pre-distorter blow-up issues.
Abstract:
A method for providing cross point information includes: providing an input signal having amplitude and phase information; interpolating between a first point of the input signal and a second point of the input signal to provide cross point information between the first point and the second point; and providing a pulse-width modulated signal based on the input signal and the cross point information.
Abstract:
Devices including a transistor having a parasitic capacitance between a control terminal and a load terminal of a first type are provided. Furthermore, the devices include advantageously arranged inductances which are electromagnetically coupled to one another and are configured at least partly to compensate for an effect of the parasitic capacitance in a range around a resonant frequency.
Abstract:
Devices including a transistor having a parasitic capacitance between a control terminal and a load terminal of a first type are provided. Furthermore, the devices include advantageously arranged inductances which are electromagnetically coupled to one another and are configured at least partly to compensate for an effect of the parasitic capacitance in a range around a resonant frequency.
Abstract:
Techniques are provided for sorting input data values using a sorting circuit. The sorting circuit includes a single stage of comparators coupled to a bank of registers. Multiplexors and a sequencer are used to route the comparator outputs back to the comparator inputs such that the comparators may be re-used over multiple sorting phases so as to order an input sequence of data values into a partially-sorted sequence or into a completely-sorted sequence that is monotonically increasing or decreasing. By re-using the comparators, the hardware required for such sorting is significantly reduced relative to conventional techniques. Also described are techniques for median filtering, which use a sorted sequence as output by the sorting circuit described herein.