公开(公告)号：US20180365181A1

公开(公告)日：2018-12-20

申请号：US15627872

申请日：2017-06-20

Applicant: Infineon Technologies AG

Inventor： Simon Cottam ,  Patrice Woodward

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F13/1642

Abstract: In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.

公开(公告)号：US20170302441A1

公开(公告)日：2017-10-19

申请号：US15486367

申请日：2017-04-13

Applicant: Infineon Technologies AG

Inventor： Christopher Temple ,  Simon Cottam ,  Frank Hellwig ,  Antonio Vilela

IPC: H04L9/06 ,  G06F21/64 ,  G06F21/85 ,  H04L9/00

CPC classification number: H04L9/0643 ,  G06F21/64 ,  G06F21/79 ,  G06F21/85 ,  H04L9/004 ,  H04L2209/127 ,  H04L2209/84

Abstract: According to various embodiments, a control device is described including an application core including a processor, a memory and a direct memory access controller and a security module coupled to the application core via a computer bus. The direct memory access controller is configured to read data from the memory, generate a hash value for the data and provide the hash value to the security module via the computer bus. The security module is configured to process the hash value.

公开(公告)号：US09727502B2

公开(公告)日：2017-08-08

申请号：US13951518

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Simon Cottam

IPC: G06F13/28 ,  G01R31/3193 ,  G06F13/42 ,  G06F13/18

CPC classification number: G06F13/28 ,  G01R31/31937 ,  G06F13/18 ,  G06F13/287 ,  G06F13/4269

Abstract: A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions.

公开(公告)号：US09703728B2

公开(公告)日：2017-07-11

申请号：US14494078

申请日：2014-09-23

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Simon Cottam

IPC: G06F12/14 ,  G06F13/28

CPC classification number: G06F12/1458 ,  G06F13/28 ,  G06F2212/1052

Abstract: A bus system includes a functional unit to which a unit identifier is assigned, a memory module for storage of data that has a storage region, and a bus. The functional unit is connected to the memory module via the bus. The storage region is configured such that one or more multiple global authorized identifiers are assigned thereto, so that the functional unit only has reading or writing access to the storage region if the unit identifier assigned to the functional unit corresponds to one of the global authorized identifiers assigned to the storage region.

公开(公告)号：US09569384B2

公开(公告)日：2017-02-14

申请号：US13803811

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Frank Hellwig ,  Simon Cottam ,  Harald Zweck

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.

Abstract translation: 一些实施例涉及直接存储器访问（DMA）控制器。 DMA控制器包括具有系统总线接口并被配置为经由系统总线接口从存储器位置读取模式的总线控制器。 图案比较逻辑将读取图案与至少一个预定图案进行比较。 如果读取模式与预定模式不同，则控制逻辑引起总线控制器处理系统总线接口上的第一条件链路，并且如果读取模式与系统总线接口不同，则总线控制器通过系统总线接口处理第二条件链路 预定模式。

公开(公告)号：US09128838B2

公开(公告)日：2015-09-08

申请号：US13957851

申请日：2013-08-02

Applicant: Infineon Technologies AG

Inventor： Antonio Vilela ,  Simon Cottam

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  G06F11/22 ,  G06F11/277

CPC classification number: G06F11/0772 ,  G06F11/16 ,  G06F11/1637 ,  G06F11/1654 ,  G06F11/167 ,  G06F11/1675 ,  G06F11/2221 ,  G06F11/277 ,  G06F2201/845

Abstract: A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other.

Abstract translation: 用于直接存储器访问（DMA）操作的系统和方法提供接收DMA请求者，将接收的DMA请求者分配给多个DMA引擎中的一个或多个以用于处理所接收的DMA请求者，并且如果所接收的DMA请求者之一是 将所述安全请求者分配给所述多个DMA引擎中的至少两个DMA引擎以处理所述安全请求者，禁用用于将所述至少两个DMA引擎的至少一个DMA引擎耦合到存储器的总线接口，将所述至少两个DMA引擎的输出进行比较 所述至少两个DMA引擎，并且如果所述至少两个DMA引擎的输出的比较彼此不同，则产生错误消息。

公开(公告)号：US08996926B2

公开(公告)日：2015-03-31

申请号：US13651775

申请日：2012-10-15

Applicant: Infineon Technologies AG

Inventor： Simon Brewerton ,  Simon Cottam ,  Frank Hellwig

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1048

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.

Abstract translation: 一些实施例涉及直接存储器访问（DMA）控制器。 DMA控制器包括一组事务控制寄存器，用于接收共同描述要由DMA控制器处理的数据传输的事务控制集合的序列。 总线控制器读取和写入存储器，而DMA控制器执行第一事务控制集以完成事务控制集序列中描述的部分数据传输。 完整性检查器基于在执行第一事务控制集期间由DMA控制器实际处理的数据或地址来确定实际的错误检测码。 完整性检查器还基于实际错误检测码是否与包含在事务控制集合的顺序的第二事务控制集中的期望错误检测码相同来选择性地标记错误。