公开(公告)号：US20190252525A1

公开(公告)日：2019-08-15

申请号：US16396088

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/7782 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20180212023A1

公开(公告)日：2018-07-26

申请号：US15745417

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Cory E. WEBER ,  Rishabh MEHANDRU ,  Stephen M. CEA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L29/0673 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/66545

Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.