公开(公告)号：US20220121595A1

公开(公告)日：2022-04-21

申请号：US17561918

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: G06F13/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42 ,  G06F13/38 ,  H03K19/173

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US11237998B2

公开(公告)日：2022-02-01

申请号：US17131404

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: H01L25/065 ,  G06F13/40 ,  G06F13/42 ,  H01L23/498 ,  H01L23/00 ,  G06F13/38 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US11115025B2

公开(公告)日：2021-09-07

申请号：US15940864

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sergey Y. Shumarayev ,  David W. Mendel ,  Joel Martinez ,  Curt Wortman

IPC: H03K19/17736 ,  G06F13/42 ,  H04L7/033 ,  H01Q21/00 ,  H04L12/40

Abstract: The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.

公开(公告)号：US11075648B2

公开(公告)日：2021-07-27

申请号：US16585934

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： David W. Mendel ,  Jeffrey Erik Schulz ,  Keith Duwel ,  Huy Ngo ,  Jakob Raymond Jones

IPC: H03M9/00 ,  G06F1/12 ,  G06F13/42 ,  H03K19/17736

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

公开(公告)号：US20190044517A1

公开(公告)日：2019-02-07

申请号：US15940864

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sergey Y. Shumarayev ,  David W. Mendel ,  Joel Martinez ,  Curt Wortman

IPC: H03K19/177 ,  H04L7/033 ,  G06F13/42

Abstract: The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.

公开(公告)号：US20180181524A1

公开(公告)日：2018-06-28

申请号：US15392225

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: G06F13/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42

CPC classification number: G06F13/4045 ,  G06F13/385 ,  G06F13/42 ,  G06F13/4291 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/1431 ,  H03K19/1736 ,  H04W56/0015

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US10461011B2

公开(公告)日：2019-10-29

申请号：US15855971

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  David W. Mendel ,  Chandra M. Jha ,  Kelly P. Lofgreen

IPC: H01L23/48 ,  H01L23/367 ,  H01L21/48 ,  H01L23/373 ,  H01L25/065 ,  H01L25/00

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a first die, a second die, and an integrated heat spreader. The integrated heat spreader may include a first surface. The first surface may define a first indentation located in between the first die and the second die.

公开(公告)号：US10445278B2

公开(公告)日：2019-10-15

申请号：US15392225

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: G06F13/40 ,  G06F13/38 ,  H01L23/52 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  G06F13/42 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US20180183463A1

公开(公告)日：2018-06-28

申请号：US15392209

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： David W. Mendel ,  Jeffrey Erik Schulz ,  Keith Duwel ,  Huy Ngo ,  Jakob Raymond Jones

IPC: H03M9/00 ,  G06F1/12

CPC classification number: H03M9/00 ,  G06F1/12 ,  G06F13/4282 ,  H03K19/17744

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.