公开(公告)号：US11574172B2

公开(公告)日：2023-02-07

申请号：US16361432

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Dipanjan Sengupta ,  Jawad B. Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06N3/063 ,  G06F3/06 ,  G06N3/04

Abstract: Technologies for efficiently performing memory augmented neural network (MANN) update operations includes a device with circuitry configured to obtain a key usable to search a memory associated with a memory augmented neural network for one or more data sets. The circuitry is also configured to perform a stochastic associative search to identify a group of data sets within the memory that satisfy the key and write to the identified group of data sets concurrently to update the memory augmented neural network.

公开(公告)号：US11507773B2

公开(公告)日：2022-11-22

申请号：US16914303

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Theodore Willke ,  Javier Sebastian Turek

IPC: G06K9/62 ,  H04L9/06 ,  G06N20/00

Abstract: Systems, apparatuses and methods may store a plurality of classes that represent a plurality of clusters in a cache. Each of the classes represents a group of the plurality of clusters and the plurality of clusters is in a first data format. The systems, apparatuses and methods further modify input data from a second data format to the first data format and conduct a similarity search based on the input data in the first data format to assign the input data to at least one class of the classes.

公开(公告)号：US20220357951A1

公开(公告)日：2022-11-10

申请号：US17872927

申请日：2022-07-25

Applicant: Intel Corporation

Inventor： Vy Vo ,  Dipanjan Sengupta ,  Mariano Tepper ,  Javier Sebastian Turek

IPC: G06F9/32 ,  G06F9/50 ,  G06F12/0815 ,  G06K9/62 ,  G06N3/063 ,  G06N3/04 ,  G06F11/34

Abstract: An example system includes memory; a central processing unit (CPU) to execute first operations; in-memory execution circuitry in the memory; and detector software to cause offloading of second operations to the in-memory execution circuitry, the in-memory execution circuitry to execute the second operations in parallel with the CPU executing the first operations.

公开(公告)号：US20200327118A1

公开(公告)日：2020-10-15

申请号：US16914302

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Nesreen K. Ahmed ,  Dipanjan Sengupta ,  Todd Anderson ,  Theodore Willke

IPC: G06F16/248 ,  G06F16/901 ,  G06K9/62 ,  G06F8/41

Abstract: Systems, apparatuses and methods may provide for technology that identifies a query code, translates the query code into a query graph, generates a candidate vector based on a candidate graph, wherein the candidate graph is associated with a candidate code, generates a query vector based on the query graph, and determines a similarity measurement between the query vector and the candidate vector.

公开(公告)号：US20200301828A1

公开(公告)日：2020-09-24

申请号：US16894180

申请日：2020-06-05

Applicant: Intel Corporation

Inventor： Jawad Khan ,  Chetan Chauhan ,  Rajesh Sundaram ,  Sourabh Dongaonkar ,  Sandeep Guliani ,  Dipanjan Sengupta ,  Mariano Tepper

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/40

Abstract: Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.

公开(公告)号：US20200265098A1

公开(公告)日：2020-08-20

申请号：US16870003

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson ,  Rajesh Sundaram

IPC: G06F16/903 ,  G06K9/62 ,  G06F17/16

Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

公开(公告)号：US20190311254A1

公开(公告)日：2019-10-10

申请号：US16448021

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Javier S. Turek ,  Dipanjan Sengupta ,  Jawad B. Khan ,  Theodore L. Willke

IPC: G06N3/063 ,  G06N3/08 ,  G06T7/11

Abstract: Technologies for performing in-memory training data augmentation for artificial intelligence include a memory comprising media access circuitry connected to a memory media. The media access circuitry is to obtain an input training data set that includes an initial amount of data samples that are usable to train a neural network. The media access circuitry is further to produce, from the input training data set, an augmented training data set with more data samples than the input training data set.

公开(公告)号：US20190220735A1

公开(公告)日：2019-07-18

申请号：US16361432

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Dipanjan Sengupta ,  Jawad B. Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06N3/063 ,  G06N3/04 ,  G06F3/06

CPC classification number: G06N3/063 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06N3/0472

Abstract: Technologies for efficiently performing memory augmented neural network (MANN) update operations includes a device with circuitry configured to obtain a key usable to search a memory associated with a memory augmented neural network for one or more data sets. The circuitry is also configured to perform a stochastic associative search to identify a group of data sets within the memory that satisfy the key and write to the identified group of data sets concurrently to update the memory augmented neural network.

公开(公告)号：US11829376B2

公开(公告)日：2023-11-28

申请号：US16868069

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Jawad Khan ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Richard Coulson ,  Theodore Willke

IPC: G06F16/2458 ,  G06N20/00 ,  G06F16/248 ,  G06N7/01

CPC classification number: G06F16/2462 ,  G06F16/248 ,  G06N7/01 ,  G06N20/00

Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.

公开(公告)号：US11500887B2

公开(公告)日：2022-11-15

申请号：US17227045

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Sourabh Dongaonkar ,  Jawad B. Khan ,  Chetan Chauhan ,  Dipanjan Sengupta ,  Mariano Tepper ,  Theodore Willke ,  Richard L. Coulson

IPC: G06F16/24 ,  G06F16/2458 ,  G06N7/00 ,  G06F16/21 ,  G06F16/22 ,  G06F16/248

Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.