公开(公告)号：US20210090207A1

公开(公告)日：2021-03-25

申请号：US17061296

申请日：2020-10-01

Applicant: Intel Corporation

Inventor： MICHAEL DOYLE ,  TRAVIS SCHLUESSLER ,  GABOR LIKTOR ,  ATSUO KUWAHARA ,  JEFFERSON AMSTUTZ

IPC: G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20200211261A1

公开(公告)日：2020-07-02

申请号：US16235744

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： SCOTT JANUS ,  PRASOONKUMAR SURTI ,  KARTHIK VAIDYANATHAN ,  GABOR LIKTOR ,  CARSTEN BENTHIN ,  PHILIP LAWS

IPC: G06T15/06 ,  G06T17/00

Abstract: Apparatus and method for general ray tracing queries. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes associated with a graphics scene; traversal/intersection hardware logic to traverse one or more rays through the acceleration data structure to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; shape processing hardware logic to specify three dimensional (3D) shape data indicating one or more 3D shapes to be used to perform queries with respect to the hierarchical acceleration data structure; query processing hardware logic to execute queries comprising comparisons between nodes of the hierarchical acceleration data structure and the 3D shape data to generate a result indicating overlap between the 3D shapes and the nodes.

公开(公告)号：US20200211147A1

公开(公告)日：2020-07-02

申请号：US16236305

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MICHAEL DOYLE ,  TRAVIS SCHLUESSLER ,  GABOR LIKTOR ,  ATSUO KUWAHARA ,  JEFFERSON AMSTUTZ

IPC: G06T1/20 ,  G06T15/00 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20190340812A1

公开(公告)日：2019-11-07

申请号：US15972644

申请日：2018-05-07

Applicant: Intel Corporation

Inventor： VALENTIN FUETTERLING ,  GABOR LIKTOR ,  KARTHIK VAIDYANATHAN

IPC: G06T17/20 ,  G06T7/20 ,  G06T15/00 ,  G06T9/00 ,  G06T19/20

Abstract: A system and method for adaptive hierarchical tessellation. For example, one embodiment of a method comprises: a tessellation queue to store portions of a first image frame to be tessellated; motion vector analysis circuitry to group a plurality of sub-tiles within each of a plurality of tiles at multiple levels of granularity, wherein the sub-tiles of a first level comprise pixels and the sub-tiles of each successive level comprise tiles from a previous level, the motion vector analysis circuitry to iteratively analyze motion vectors of each group of sub-tiles at each level of granularity to determine whether the motion vectors are similar in accordance with a defined threshold, the motion vector analysis circuitry to queue tiles having sub-tiles which are determined to be dissimilar to the tessellation queue.

公开(公告)号：US20210201558A1

公开(公告)日：2021-07-01

申请号：US16728375

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： KAROL SZERSZEN ,  PRASOONKUMAR SURTI ,  GABOR LIKTOR ,  KARTHIK VAIDYANATHAN ,  SVEN WOOP

IPC: G06T15/06 ,  G06T15/08 ,  G06T15/00 ,  G06T17/10 ,  G06T1/20

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US20210150800A1

公开(公告)日：2021-05-20

申请号：US17108774

申请日：2020-12-01

Applicant: Intel Corporation

Inventor： CARSTEN BENTHIN ,  INGO WALD ,  GABOR LIKTOR ,  JOHANNES GUENTHER ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06T15/06 ,  G06T15/00 ,  G06T9/00 ,  G06T9/40

Abstract: An apparatus and method for performing BVH compression and decompression concurrently with stores and loads, respectively. For example, one embodiment comprises: bounding volume hierarchy (BVH) construction circuitry to build a BVH based on a set of input primitives, the BVH comprising a plurality of uncompressed coordinates; traversal/intersection circuitry to traverse one or more rays through the BVH and determine intersections with the set of input primitives using the uncompressed coordinates; store with compression circuitry to compress the BVH including the plurality of uncompressed coordinates to generate a compressed BVH with compressed coordinates and to store the compressed BVH to a memory subsystem; and load with decompression circuitry to decompress the BVH including the compressed coordinates to generate a decompressed BVH with the uncompressed coordinates and to load the decompressed BVH with uncompressed coordinates to a cache and/or a set of registers accessible by the traversal/intersection circuitry.

公开(公告)号：US20200211260A1

公开(公告)日：2020-07-02

申请号：US16235583

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： KAI XIAO ,  MICHAEL APODACA ,  CARSON BROWNLEE ,  THOMAS RAOUX ,  JOSHUA BARCZAK ,  GABOR LIKTOR

IPC: G06T15/06 ,  G06T1/20

Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

公开(公告)号：US20150379763A1

公开(公告)日：2015-12-31

申请号：US14319130

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： GABOR LIKTOR ,  MARCO SALVI ,  KARTHIK VAIDYANATHAN

IPC: G06T15/80 ,  G06T1/60 ,  G06K9/52 ,  G06T1/20 ,  G06T17/10

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T15/005 ,  G06T15/04

Abstract: An apparatus and method for performing coarse pixel shading (CPS). For example, one embodiment of a method comprises: A method for coarse pixel shading (CPS) comprising: pre-processing a graphics mesh by creating a tangent-plane parameterization of desired vertex attributes for each vertex of the mesh; and performing rasterization of the mesh in a rasterization stage of a graphics pipeline using the tangent-plane parameterization.

Abstract translation: 一种用于执行粗略像素阴影（CPS）的设备和方法。 例如，一种方法的一个实施例包括：一种用于粗略像素着色（CPS）的方法，包括：通过为所述网格的每个顶点创建所需顶点属性的切平面参数化来预处理图形网格; 以及使用切平面参数化在图形管线的光栅化阶段中执行网格的光栅化。