公开(公告)号：US10367070B2

公开(公告)日：2019-07-30

申请号：US15754804

申请日：2015-09-24

申请人： Intel Corporation ,  Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

发明人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC分类号： H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/417 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

摘要： Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

公开(公告)号：US20180248012A1

公开(公告)日：2018-08-30

申请号：US15754804

申请日：2015-09-24

申请人： Intel Corporation

发明人： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC分类号： H01L29/417 ,  H01L29/08 ,  H01L23/528 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L29/41791 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.