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公开(公告)号：US09870047B2
公开(公告)日：2018-01-16
申请号：US15192134
申请日：2016-06-24
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US09128842B2
公开(公告)日：2015-09-08
申请号：US13631625
申请日：2012-09-28
Applicant: Intel Corporation
Inventor： Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Sadagopan Srinivasan
CPC classification number: G06F12/08 , G06F12/0891
Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.
Abstract translation: 描述了具有高速缓存电路和逻辑电路的处理器。 逻辑电路是管理高速缓存线路的高速缓存行的输入和移除。 逻辑电路包括存储电路和控制电路。 存储电路用于存储标识高速缓存中处于修改状态的一组高速缓存行的信息。 控制电路耦合到存储电路，以响应于刷新高速缓存的信号从存储电路接收信息，并从其中确定高速缓存的地址，从而从高速缓存读取高速缓存行集合，以避免 从缓存中读取处于无效或干净状态的缓存行。
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公开(公告)号：US20230327960A1
公开(公告)日：2023-10-12
申请号：US18210478
申请日：2023-06-15
Applicant: Intel Corporation
Inventor： Mrittika Ganguli , Muthuvel M. I , Ananth S. Narayan , Jaideep Moses , Andrew J. Herdrich , Rahul Khanna
IPC: H04L41/50 , H04L41/5025 , H04L41/14 , H04L41/5009
CPC classification number: H04L41/50 , H04L41/5009 , H04L41/145 , H04L41/5025
Abstract: In accordance with some embodiments, a cloud service provider may operate a data center in a way that dynamically reallocates resources across nodes within the data center based on both utilization and service level agreements. In other words, the allocation of resources may be adjusted dynamically based on current conditions. The current conditions in the data center may be a function of the nature of all the current workloads. Instead of simply managing the workloads in a way to increase overall execution efficiency, the data center instead may manage the workload to achieve quality of service requirements for particular workloads according to service level agreements.
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Patent Agency Ranking
公开(公告)号：US20190238416A1
公开(公告)日：2019-08-01
申请号：US16200956
申请日：2018-11-27
Applicant: Intel Corporation
Inventor： Mats Agerstam , Robert A. Colby , Jaideep Moses , Patrick C. Lankswert
Abstract: A method for discovery of devices is described herein. The method includes connecting, via a processor, to a discovery node service. The method also includes sending, via the processor, a node name to the discovery node service. The method further includes sending, via the processor, data and content to be sent to a discovery node associated with the node name. The method also further includes receiving data and content from the discovery node, the data to include a list of devices subscribed to the discovery node.
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公开(公告)号：US10148514B2
公开(公告)日：2018-12-04
申请号：US14581674
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Mats Agerstam , Robert A. Colby , Jaideep Moses , Patrick C. Lankswert
Abstract: A method for discovery of devices is described herein. The method includes connecting, via a processor, to a discovery node service. The method also includes sending, via the processor, a node name to the discovery node service. The method further includes sending, via the processor, data and content to be sent to a discovery node associated with the node name. The method also further includes receiving data and content from the discovery node, the data to include a list of devices subscribed to the discovery node.
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公开(公告)号：US20160299558A1
公开(公告)日：2016-10-13
申请号：US15134756
申请日：2016-04-21
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US10048743B2
公开(公告)日：2018-08-14
申请号：US15134756
申请日：2016-04-21
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC: G06F1/32 , G06F12/08 , G06F9/44 , H04W88/02 , G06F13/24 , G06F9/50 , G06F9/4401 , H04W52/02 , G06F12/084
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US09864427B2
公开(公告)日：2018-01-09
申请号：US15134770
申请日：2016-04-21
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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