公开(公告)号：US09436605B2

公开(公告)日：2016-09-06

申请号：US14136131

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0815

Abstract: An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.

Abstract translation: 一种用于减少或消除写回操作的设备和方法。 例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

公开(公告)号：US20150095580A1

公开(公告)日：2015-04-02

申请号：US14040375

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Bahaa Fahim ,  Erik G. Hallnor ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren ,  Antonio Juan

IPC: G06F12/08

Abstract: A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.

Abstract translation: 处理器包括对应于分布式高速缓存的第一高速缓存部分的高速缓存器侧地址监视器单元，其具有小于处理器的逻辑处理器总数的高速缓存器侧地址监视器存储位置的总数。 每个缓存侧地址监视器存储位置是存储要监视的地址。 核心侧地址监视器单元对应于第一核心，并且具有与第一核心的多个逻辑处理器相同数量的核心侧地址监视器存储位置。 每个核心侧地址监视器存储位置用于存储第一核心的不同对应逻辑处理器的地址和监视状态。 高速缓存侧地址监视器存储溢出单元对应于第一高速缓存部分，并且当没有未使用的高速缓存侧地址监视器存储位置可用于存储要监视的地址时，强制执行地址监视器存储溢出策略。

公开(公告)号：US12066939B2

公开(公告)日：2024-08-20

申请号：US17086243

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Rahul R. Shah ,  Omkar Maslekar ,  Priya Autee ,  Edwin Verplanke ,  Andrew J. Herdrich ,  Jeffrey D. Chamberlain

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1009

CPC classification number: G06F12/0811 ,  G06F9/30047 ,  G06F9/30079 ,  G06F12/084 ,  G06F12/1009

Abstract: Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

公开(公告)号：US11922220B2

公开(公告)日：2024-03-05

申请号：US17255588

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Mohammad R. Haghighat ,  Kshitij Doshi ,  Andrew J. Herdrich ,  Anup Mohan ,  Ravishankar R. Iyer ,  Mingqiu Sun ,  Krishna Bhuyan ,  Teck Joo Goh ,  Mohan J. Kumar ,  Michael Prinke ,  Michael Lemay ,  Leeor Peled ,  Jr-Shian Tsai ,  David M. Durham ,  Jeffrey D. Chamberlain ,  Vadim A. Sukhomlinov ,  Eric J. Dahlen ,  Sara Baghsorkhi ,  Harshad Sane ,  Areg Melik-Adamyan ,  Ravi Sahita ,  Dmitry Yurievich Babokin ,  Ian M. Steiner ,  Alexander Bachmutsky ,  Anil Rao ,  Mingwei Zhang ,  Nilesh K. Jain ,  Amin Firoozshahian ,  Baiju V. Patel ,  Wenyong Huang ,  Yeluri Raghuram

IPC: G06F9/50 ,  G06F9/52 ,  G06F11/30 ,  G06F11/34 ,  G06F21/53 ,  G06F21/56 ,  G06F21/60 ,  G06N20/00

CPC classification number: G06F9/5061 ,  G06F9/52 ,  G06F11/302 ,  G06F11/3495 ,  G06F21/53 ,  G06F21/604 ,  G06F21/56 ,  G06F2209/521 ,  G06F2221/033 ,  G06N20/00

Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

公开(公告)号：US20210263779A1

公开(公告)日：2021-08-26

申请号：US17255588

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Mohammad R. Haghighat ,  Kshitij Doshi ,  Andrew J. Herdrich ,  Anup Mohan ,  Ravishankar R. Iyer ,  Mingqiu Sun ,  Krishna Bhuyan ,  Teck Joo Goh ,  Mohan J. Kumar ,  Michael Prinke ,  Michael Lemay ,  Leeor Peled ,  Jr-Shian Tsai ,  David M. Durham ,  Jeffrey D. Chamberlain ,  Vadim A. Sukhomlinov ,  Eric J. Dahlen ,  Sara Baghsorkhi ,  Harshad Sane ,  Areg Melik-Adamyan ,  Ravi Sahita ,  Dmitry Yurievich Babokin ,  Ian M. Steiner ,  Alexander Bachmutsky ,  Anil Rao ,  Mingwei Zhang ,  Nilesh K. Jain ,  Amin Firoozshahian ,  Baiju V. Patel ,  Wenyong Huang ,  Yeluri Raghuram

IPC: G06F9/50 ,  G06F21/53 ,  G06F9/52 ,  G06F21/60 ,  G06F11/30 ,  G06F11/34

Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

公开(公告)号：US10795853B2

公开(公告)日：2020-10-06

申请号：US15721822

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US10338974B2

公开(公告)日：2019-07-02

申请号：US14126875

申请日：2013-11-06

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain

IPC: G06F9/46 ,  G06F9/52 ,  G06F9/48

Abstract: A starvation mode is entered and a particular dependency of a first request in a retry queue is identified. The particular dependency is determined to be acquired and the first request is retried based on acquisition of the particular dependency.

公开(公告)号：US20170337134A1

公开(公告)日：2017-11-23

申请号：US15447767

申请日：2017-03-02

Applicant: Intel Corporation

Inventor： Robert G. Blankenship ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Vedaraman Geetha

IPC: G06F12/0891

CPC classification number: G06F12/0891 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/126 ,  G06F2212/1016

Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

公开(公告)号：US20170192887A1

公开(公告)日：2017-07-06

申请号：US15401220

申请日：2017-01-09

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Ravishankar Iyer ,  Christopher C. Gianos ,  Jeffrey D. Chamberlain ,  Ronak Singhal ,  Julius Mandelblat ,  Bret L. Toll

IPC: G06F12/0804 ,  G06F12/084 ,  G06F12/0897 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0842

CPC classification number: G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/604

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

公开(公告)号：US09563564B2

公开(公告)日：2017-02-07

申请号：US14680287

申请日：2015-04-07

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Ravishankar Iyer ,  Christopher C. Gianos ,  Jeffrey D. Chamberlain ,  Ronak Singhal ,  Julius Mandelblat ,  Bret L. Toll

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/604

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Abstract translation: 具有代码和数据优先级的缓存分配的系统和方法。 示例系统可以包括：高速缓存; 处理核心，可操作地耦合到高速缓存; 以及高速缓存控制逻辑，响应于接收到包括请求类型的标识符和服务等级的标识符的高速缓存填充请求，以识别对应于与请求类型和类别相关联的容量位掩码的高速缓存的子集 的服务。