公开(公告)号：US20180101207A1

公开(公告)日：2018-04-12

申请号：US15695947

申请日：2017-09-05

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  Srikrishnan Venkataraman ,  William J. Lambert ,  Michael J. Hill ,  Alexander Slepoy ,  Dong Zhong ,  Kaladhar Radhakrishnan ,  Hector A. Aguirre Diaz ,  Jonathan P. Douglas

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H01L23/645 ,  H02J1/00 ,  H02M1/14 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/008 ,  H02M2003/1586

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

公开(公告)号：US20170005670A1

公开(公告)日：2017-01-05

申请号：US15265730

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Takao Oshita ,  George L. Geannopoulos ,  David E. Duarte ,  J. Keith Hodgson ,  James S. Ayers ,  Avner Kornfeld ,  Jonathan P. Douglas

IPC: H03M3/00 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M3/458 ,  H03M1/00 ,  H03M1/002 ,  H03M1/12 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/804 ,  H03M3/30 ,  H03M3/32 ,  H03M3/34

Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Abstract translation: 描述了一种模数转换器（ADC），其包括：用于接收模拟信号的Σ-Δ调制器，可用于执行斩波以消除共模噪声的Σ-Δ调制器; 以及耦合到Σ-Δ调制器的一个或多个计数器以产生表示模拟信号的数字代码。

公开(公告)号：US20220375898A1

公开(公告)日：2022-11-24

申请号：US17323094

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Vishram Shriram Pandit ,  Narayanan Natarajan ,  Jayanth M. Kalyan ,  Khondker Z. Ahmed ,  Jonathan P. Douglas ,  Gururaj K. Shamanna ,  Chin Lee Kuan

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48

Abstract: An Integrated Circuit (IC) package is provided, comprising a first IC die having a first capacitor and a logic circuit, and a second IC die having a second capacitor. The first IC die and the second IC die may be stacked within the IC package one on top of another and electrically coupled with die-to-die interconnects. The logic circuit is electrically coupled in a power delivery network to the first capacitor and the second capacitor. The first IC die and the second IC die include respective back-end-of-line portions in which the first capacitor and the second capacitor, which may comprise metal-insulator-metal capacitors in some embodiments are situated. In some embodiments, the second capacitor is situated in a shadow of the logic circuit. In various embodiments, the first IC die and the second IC die comprise any suitable pair in a plurality of stacked IC dies within an IC package.

公开(公告)号：US10033402B2

公开(公告)日：2018-07-24

申请号：US15265730

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Takao Oshita ,  George L. Geannopoulos ,  David E. Duarte ,  J. Keith Hodgson ,  James S. Ayers ,  Avner Kornfeld ,  Jonathan P. Douglas

IPC: H03M3/00 ,  H03M1/00 ,  H03M1/12 ,  H03M1/80

Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

公开(公告)号：US20170060205A1

公开(公告)日：2017-03-02

申请号：US14836780

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Srikrishnan Venkataraman ,  William J. Lambert ,  Michael J. Hill ,  Alexander Slepoy ,  Dong Zhong ,  Kaladhar Radhakrishnan ,  Hector A. Aguirre Diaz ,  Jonathan P. Douglas

IPC: G06F1/26 ,  H02J1/00 ,  G06F1/32 ,  H02M3/158

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H01L23/645 ,  H02J1/00 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/008 ,  H02M2003/1586

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract translation: 描述了一种装置，其包括：耦合到第一一个或多个电感器的第一电压调节器（VR），第一VR为第一功率域提供电力; 以及耦合到第二一个或多个电感器的第二VR，其中至少一个电感器感应耦合到所述第一个或多个电感器中的至少一个，所述第二VR为与所述第一电源域分离的第二电力域提供电力， 其中在第一VR相对于第二VR的开关晶体管之间存在非零相位角偏移。